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[ak4646] ms0557-e-05 2011/01 - 1 - general description the ak4646 features a stereo code c with a built-in microphone-amplif ier and speaker-amplifier. input circuits include a microphone-amplifier and an alc (aut o level control) circui t, and output circuits include a speaker-amplifier. these ci rcuits are suitable for portable app lication with recording/playback function. the ak4646 is available in a small 32pin qfn (5mmx5mm: ak4646en, 4mmx4mm: ak4646ez), utilizing less board spac e than competitive offerings. features 1. recording function ? stereo mic input (full-di fferential or single-ended) ? stereo line input ? mic amplifier (+32db/+29db/+26d b/+23db/+20db/+ 17db/+10db/0db) ? digital alc (automatic level control) (+36db ? 54db, 0.375db step, mute) ? adc performance: s/(n+d): 83db, dr, s/n: 86db (mic-amp=+20db) s/(n+d): 88db, dr, s/n: 95db (mic-amp=0db) ? wind-noise reduction filter ? 5 band notch filter ? stereo separation emphasis 2. playback function ? digital de-emphasis filter (tc=50/15 s, fs=32khz, 44.1khz, 48khz) ? digital alc (automatic level control) (+36db ? 54db, 0.375db step, mute) ? stereo separation emphasis ? stereo line output - performance: s/(n+d): 88db, s/n: 92db ? mono speaker-amp - s/(n+d): 60db@150mw, s/n: 90db - btl output - available for both dynamic and piezo speaker - output power: 400mw@8 (svdd=3.3v) ? analog mixing: mono input 3. power management 4. master clock: (1) pll mode ? frequencies: 12mhz, 13.5mhz, 24mhz, 27mhz (mcki pin) 1fs (lrck pin) 32fs or 64fs (bick pin) (2) external clock mode ? frequencies: 256fs, 512fs or 1024fs (mcki pin) 5. output master clock fr equencies: 32fs/64fs/128fs/256fs stereo codec with mic/spk- a mp ak4646
[ak4646] ms0557-e-05 2011/01 - 2 - 6. sampling rate: ? pll slave mode (lrck pin): 7.35khz 48khz ? pll slave mode (bick pin): 7.35khz 48khz ? pll slave mode (mcki pin): 8khz, 11.025khz, 12khz, 16khz, 22.05kh z, 24khz, 32khz, 44.1khz, 48khz ? pll master mode: 8khz, 11.025khz, 12khz, 16khz, 22.05kh z, 24khz, 32khz, 44.1khz, 48khz ? ext slave mode: 7.35khz 48khz (256fs), 7.35khz 26khz (512fs), 7.35khz 13khz (1024fs) 7. p i/f: 3-wire serial 8. master/slave mode 9. audio interface format: msb first, 2?s compliment ? adc: 16bit msb justified, i 2 s ? dac: 16bit msb justified, 16bit lsb justified, 16-24bit i 2 s 10. ta = ? 30 85 c 11. power supply: ? avdd: 2.2 3.6v (typ. 3.3v) ? dvdd: 1.6 3.6v (typ. 3.3v) ? svdd: 2.2 4.0 v (typ. 3.3v) 12. power supply current: 19ma 13. package: 32pin qfn, 5mm x 5mm, 0.5mm pitch (ak4646en) 32pin qfn, 4mm x 4mm, 0.4mm pitch (ak4646ez) 14. pin/register compatible with ak4642en/ak4643en (ak4646en) block diagram mic power supply mic-amp a/d stereo separation hpf pmadl pmadr pmmp pmadl or pmadr audio i/f d/a datt smute pmdac internal mic external mic line out pmspk speaker alc pll pmbp pmpll control register mpwr lin1 rin1 lin2 rin2 spp spn svdd svss min avdd a vss vcom dvdd cclk pdn cdtio bick lrck sdto sdti mcko mcki vcoc pmlo lout rout dvss csn 5 band eq dem pmadcl or pmadcr or pmdac lpf hpf figure 1. block diagram
[ak4646] ms0557-e-05 2011/01 - 3 - ordering guide ak4646en ? 30 +85 c 32pin qfn (0.5mm pitch) ak4646ez ? 30 +85 c 32pin qfn (0.4mm pitch) akd4646 evaluation board for ak4646 pin layout ak4646en/ez nc rout lout min rin2 / in2 ? lin2 / in2+ lin1 / in1 ? rin1 / in1+ nc nc svss svdd spp spn mcko mc ki mpwr vcom avss avdd vc oc nc pdn csn dvss dvdd bick lrck sdto sdti cdtio cclk ak4646 top view 25 2 6 27 28 29 30 31 32 24 23 22 1 16 1 5 14 13 12 11 10 9 21 20 19 18 17 2 3 4 5 6 7 8
[ak4646] ms0557-e-05 2011/01 - 4 - comparison with ak4642/ak4643 1. function function ak4642 ak4643 ak4646 avdd 2.6v 3.6v 2.2v 3.6v dvdd 2.6v 3.6v 1.6v 3.6v power supply for spk-amp 2.6v 5.25v (hvdd) 2.2v 4.0v (svdd) output voltage of mic power 0.75 x avdd 0.8 x avdd mic-amp 0db/+20db/+26db/+32db 0db/+10db/+17db/+20db/ +23db/+26db/+29db/ +32db hpf / lpf 1 step hpf : 2 step, lpf : 1 step notch filter no 5 band alc recovery operation waiting period 128/fs 1024/fs 128/fs 16384/fs 128/fs 16384/fs read of alc volume no no yes output volume +12db -115db, 0.5db step +36db -54db, 0.375db step ( note 1 ) 0db -18db, 6db step headphone-amp yes no bass boost yes no receiver-amp no yes no spk-amp output power 400mw@3.3v 1.2w@5v 400mw@3.3v analog mixing 1 mono 2 stereo 1 mono adc input selector 2 stereo 3 stereo 2 stereo spk-amp maximum output voltage for piezo speaker 8.5vpp@svdd=5v 6.33vpp@svdd=3.8v p i/f 3-wire(write only), i2c-bus 3-wire(read/write) audio i/f format dsp mode no yes no ext master mode no yes no master clock frequency for pll mode 11.2896mhz, 12mhz, 12.288mhz, 13.5mhz 24mhz, 27mhz 12mhz, 13.5mhz, 24mhz, 27mhz note 1. alc and volume circuits are shared by input and output. therefore, it is impossible to use alc and volume function at same time for both recording and playback mode.
[ak4646] ms0557-e-05 2011/01 - 5 - pin/function no. pin name i/o function 1 mpwr o mic power supply pin 2 vcom o common voltage output pin, 0.5 x avdd bias voltage of adc inputs and dac outputs. 3 avss - analog ground pin 4 avdd - analog power supply pin 5 vcoc o output pin for loop filter of pll circuit this pin should be connected to avss with one resistor and capacitor in series. 6 nc - no connect pin no internal bonding. this pin should be connected to ground. 7 pdn i power-down mode pin ?h?: power-up, ?l?: power-down, reset and initializes the control register. 8 csn i chip select pin 9 cclk i control data clock pin 10 cdtio i/o control data input and output pin 11 sdti i audio serial data input pin 12 sdto o audio serial data output pin 13 lrck i/o input / output channel clock pin 14 bick i/o audio serial data clock pin 15 dvdd - digital power supply pin 16 dvss - digital ground pin 17 mcki i external master clock input pin 18 mcko o master clock output pin 19 spn o speaker amp negative output pin 20 spp o speaker amp positive output pin 21 svdd - speaker amp power supply pin 22 svss - speaker amp ground pin 23 24 25 nc - no connect pin no internal bonding. this pin should be connected to ground or open. 26 rout o rch stereo line output pin 27 lout o lch stereo line output pin 28 min i mono signal input pin rin2 i rch analog input 2 pin (mdif2 bit = ?0?, single-ended input) 29 in2 ? i microphone negative input 2 pin (mdif2 bit = ?1?, full-differential input) lin2 i lch analog input 2 pin (mdif2 bit = ?0?, single-ended input) 30 in2+ i microphone positive input 2 pin (mdi f2 bit = ?1?, full-differential input) lin1 i lch analog input 1 pin (mdif1 bit = ?0?, single-ended input) 31 in1 ? i microphone negative input 1 pin (mdif1 bit = ?1?, full-differential input) rin1 i rch analog input 1 pin (mdif1 bit = ?0?, single-ended input) 32 in1+ i microphone positive input 1 pin (mdi f1 bit = ?1?, full-differential input) note 2. all input pins except analog input pins (min, lin1, rin1, lin2, rin2) should not be left floating.
[ak4646] ms0557-e-05 2011/01 - 6 - handling of unused pin the unused i/o pins should be processed appropriately as below. classification pin name setting analog mpwr, vcoc, spn, spp, rout, lout, min, rin2/in2 ? , lin2/in2+, lin1/in1 ? , rin1/in1+ these pins should be open. digital mcko this pin should be open. mcki this pin should be connected to dvss.
[ak4646] ms0557-e-05 2011/01 - 7 - absolute maximum ratings (avss=dvss=svss=0v; note 3 ) parameter symbol min max units power supplies: analog avdd ? 0.3 4.6 v digital dvdd ? 0.3 4.6 v speaker-amp svdd ? 0.3 4.6 v |avss ? dvss| ( note 4 ) gnd1 - 0.3 v |avss ? svss| ( note 4 ) gnd2 - 0.3 v input current, any pin except supplies iin - 10 ma analog input voltage ( note 5 ) vina ? 0.3 avdd+0.3 v digital input voltage ( note 6 ) vind ? 0.3 dvdd+0.3 v ak4646en ta ? 30 85 c ( note 7 ) ta ? 30 85 c ambient temperature (powered applied) ak4646ez ( note 8 ) ta ? 30 70 c storage temperature tstg ? 65 150 c maximum power dissipation ( note 9 ) pd1 - 450 mw note 3. all voltages are with respect to ground. note 4. avss, dvss and svss must be connected to the same analog ground plane. note 5.min, rin2/in2 ? , lin2/in2+, lin1/in1 ? , rin1/in1+ pins note 6. pdn, csn, cclk, cdtio, sdti, lrck, bick, mcki pins pull-up resistors at sda and scl pins should be connected to dvdd or less voltage. note 7. when the exposed pad on the bottom surf ace of the package is c onnected to the ground. note 8. when the exposed pad on the bottom surface of the package is open. note 9. in case that pcb wiring density is 100%. this power is the ak4646 internal dissipation that does not include power of externally connected speaker. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guara nteed at these extremes. recommended operating conditions (avss=dvss=svss=0v; note 3 ) parameter symbol min typ max units power supplies analog avdd 2.2 3.3 3.6 v ( note 10 ) digital dvdd 1.6 3.3 3.6 v spk-amp ( note 11 ) svdd 2.2 3.3 4.0 v difference dvdd ? avdd - - +0.3 v dvdd ? svdd - - +0.3 v avdd ? svdd - - +0.8 v note 3. all voltages are with respect to ground. note 10. the power-up sequence between avdd, dvdd and svdd is not critical. when avdd or svdd is powered off, the power supply current of dvdd at power-down mode may be increased. when the power supplies are partially powered off, the ak4646 must be reset by bringing pdn pin ?l? after these power supplies are powered on again. note 11. svdd = 2.2 3.6v when 8 dynamic speaker is connected to the ak4646. * akm assumes no responsibility for the usage beyond the conditions in this datasheet.
[ak4646] ms0557-e-05 2011/01 - 8 - analog characteristics (ta=25 c; avdd=dvdd=svdd=3.3v; avss=dvss=svss= 0v; fs=44.1khz, bick=64fs; signal frequency=1khz; 16bit data; measurement frequency=20hz 20khz; unless otherwise specified) parameter min typ max units mic amplifier: lin1, rin1, lin2, rin2 pins; mdif1 = mdif2 bits = ? 0 ? (single-ended inputs) input resistance 20 30 40 k mgain2-0 bits = ?000? - 0 - db mgain2-0 bits = ?001? - +20 - db mgain2-0 bits = ?010? - +26 - db gain mgain2-0 bits = ?011? - +32 - db mgain2-0 bits = ?100? - +10 - db mgain2-0 bits = ?101? - +17 - db mgain2-0 bits = ?110? - +23 - db mgain2-0 bits = ?111? - +29 - db mic amplifier: in1+, in1 ? , in2+, in2 ? pins; mdif1 = mdif2 bits = ? 1 ? (full-differential input) input voltage ( note 12 ) mgain2-0 bits = ?001? - - 0.242 vpp mgain2-0 bits = ?010? - - 0.121 vpp mgain2-0 bits = ?011? - - 0.061 vpp mgain2-0 bits = ?100? - - 0.765 vpp mgain2-0 bits = ?101? - - 0.342 vpp mgain2-0 bits = ?110? - - 0.171 vpp mgain2-0 bits = ?111? - - 0.086 vpp mic power supply: mpwr pin output voltage ( note 13 ) 2.38 2.64 2.90 v load resistance 0.5 - - k load capacitance - - 30 pf adc analog input characteristics: lin1/rin1/lin2/rin2 pins adc ivol, ivol=0db, alc=off resolution - - 16 bits ( note 15 ) 0.178 0.210 0.242 vpp input voltage ( note 14 ) ( note 16 ) 1.78 2.10 2.42 vpp ( note 15 ) 73 83 - dbfs s/(n+d) ( ? 1dbfs) ( note 16 ) - 88 - dbfs ( note 15 ) 76 86 - db d-range ( ? 60dbfs, a-weighted) ( note 16 ) - 95 - db ( note 15 ) 76 86 - db s/n (a-weighted) ( note 16 ) - 95 - db ( note 15 ) 75 90 - db interchannel isolation ( note 16 ) - 100 - db ( note 15 ) - 0.1 0.8 db interchannel gain mismatch ( note 16 ) - 0.1 0.8 db note 12. the voltage difference between in1/2+ and in1/2 ? pins. ac coupling capacitor should be inserted in series at each input pin. full-differential mic i nput is not available at mgain2-0 b its = ?000?. maximum input voltage of in1+, in1 ? , in2+ and in2 ? pins is proportional to avdd voltage, respectively. vin = |(in1/2+) ? (in1/2 ? )| = 0.073 x avdd (max)@mgain2-0 bits = ? 001 ? , 0.037 x avdd (max)@mgain2-0 bits = ? 010 ? , 0.018 x avdd (max)@mgain2-0 bits = ? 011 ? , 0.232 x avdd (max)@mgain2-0 bits = ? 100 ? , 0.104 x avdd (max)@mgain2-0 bits = ? 101 ? , 0.052 x avdd (max)@mgain2-0 bits = ? 110 ? , 0.026 x avdd (max)@mgain2-0 bits = ? 111 ? note 13. output voltage is proportional to avdd voltage. vout = 0.8 x avdd (typ) note 14. input voltage is proportional to avdd voltage vin = 0.0636 x avdd (typ)@mgain2-0 bits = ? 001 ? (+20db), vin = 0.636 x avdd (typ)@mgain2-0 bits = ? 000 ? (0db) note 15. mgain2-0 bits = ? 001 ? (+20db) note 16. mgain2-0 bits = ? 000 ? (0db)
[ak4646] ms0557-e-05 2011/01 - 9 - parameter min typ max units dac characteristics: resolution - - 16 bits stereo line output characteristics: dac lout, rout pins, alc=off, ovol=0db, lovl1-0 bit = ?00?, r l =10k output voltage ( note 17 ) lovl1-0 bit = ?00? 1.78 1.98 2.18 vpp lovl1-0 bit = ?01? 2.25 2.50 2.75 vpp s/(n+d) ( ? 3dbfs) 78 88 - dbfs s/n (a-weighted) 82 92 - db interchannel isolation 85 100 - db interchannel gain mismatch - 0.1 0.8 db load resistance 10 - - k load capacitance - - 30 pf speaker-amp characteristics: dac spp/spn pins, alc=off, ovol=0db, r l =8 , btl, svdd=3.3v output voltage ( note 18 ) spkg1-0 bits = ?00?, ? 0.5dbfs (po=150mw) - 3.18 - vpp spkg1-0 bits = ?01?, ? 0.5dbfs (po=250mw) 3.20 4.00 4.80 vpp spkg1-0 bits = ?10?, ? 0.5dbfs (po=400mw) - 1.79 - vrms s/(n+d) spkg1-0 bits = ?00?, ? 0.5dbfs (po=150mw) - 60 - db spkg1-0 bits = ?01?, ? 0.5dbfs (po=250mw) 20 50 - db spkg1-0 bits = ?10?, ? 0.5dbfs (po=400mw) - 20 - db s/n (a-weighted) 80 90 - db load resistance 8 - - load capacitance - - 30 pf note 17. output voltage is proportional to avdd voltage.vout = 0.6 x avdd (typ)@lovl bit = ?0?. note 18. output voltage is proportional to avdd voltage. when the dac input is -0.5dbfs in full-differential mode, vout = 0.96 x avdd (typ)@spkg1-0 bits = ?00?, 1.21 x avdd (typ)@spkg1-0 bits = ?01?, 1.52 x avdd (typ)@spkg1-0 bits = ?10?, 1.92 x avdd (typ)@spkg1-0 bits = ?11?
[ak4646] ms0557-e-05 2011/01 - 10 - parameter min typ max units speaker-amp characteristics: dac spp/spn pins, alc=off,ovol=0db, c l =3 f, r serial =10 x 2, btl, svdd=3.8v output voltage ( note 18 ) spkg1-0 bits = ?11?, -0.5dbfs - 6.33 - vpp s/(n+d) ( note 19 ) spkg1-0 bits = ?11?, -0.5dbfs - 60 - db s/n (a-weighted) - 90 - db load impedance ( note 20 ) 50 - - load capacitance ( note 20 ) - - 3 f mono input: min pin (external input resistance=20k ) maximum input voltage ( note 21 ) - 1.98 - vpp gain ( note 22 ) min ? lout/rout lovl1-0 bit = ?00? -4.5 0 +4.5 db lovl1-0 bit = ?01? - +2 - db lovl1-0 bit = ?10? - +4 - db lovl1-0 bit = ?11? - +6 - db min ? spp/spn alc bit = ?0?, spkg1-0 bits = ?00? +0.1 +4.6 +9.1 db alc bit = ?0?, spkg1-0 bits = ?01? - +6.6 - db alc bit = ?0?, spkg1-0 bits = ?10? - +8.6 - db alc bit = ?0?, spkg1-0 bits = ?11? - +10.6 - db alc bit = ?1?, spkg1-0 bits = ?00? - +6.6 - db alc bit = ?1?, spkg1-0 bits = ?01? - +8.6 - db alc bit = ?1?, spkg1-0 bits = ?10? - +10.6 - db alc bit = ?1?, spkg1-0 bits = ?11? - +12.6 - db power supplies: power up (pdn pin = ? h ? ) all circuit power-up ( note 23 ) avdd+dvdd - 15 23 ma svdd (no output) - 4 12 ma power down (pdn pin = ?l?) ( note 24 ) avdd+dvdd+svdd - 1 100 a note 19. in case of measuring at spp and spn pins. note 20. load impedance is total impedance of seri es resistance and piezo speaker impedance at 1khz in figure 34 . load capacitance is capacitance of piezo speaker. when piezo speaker is used, 10 or more series resistors should be connected at both spp and spn pins, respectively. note 21. maximum voltage is in proportion to both avdd and external input resistance (rin). vin = 0.636 x avdd x rin / 20k (typ). note 22. the gain is in inverse proportion to external input resistance note 23. pll master mode (mcki=12mhz); pmadl = pmadr = pmdac = pmlo = pmspk = pmvcm = pmpll = mcko = pmbp = pmmp = m/s bits = ?1?. mpwr pin outputs 0ma. avdd= 10ma(typ), dvdd=5ma(typ). ext slave mode (pmpll = m/s = mcko bits = ? 0 ? ): avdd=10ma(typ), dvdd=4ma(typ). note 24. all digital input pins are fixed to dvdd or dvss.
[ak4646] ms0557-e-05 2011/01 - 11 - filter characteristics (ta = 25 c; avdd =2.2 3.6v, dvdd =1.6 3.6v, svdd =2.2 4.0v; fs=44.1khz; dem=off) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 25 ) 0.16db pb 0 - 17.3 khz ? 0.66db - 19.4 - khz ? 1.1db - 19.9 - khz ? 6.9db - 22.1 - khz stopband sb 26.1 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 73 - - db group delay ( note 26 ) gd - 19 - 1/fs group delay distortion gd - 0 - s dac digital filter (lpf): passband ( note 25 ) 0.05db pb 0 - 20.0 khz ? 6.0db - 22.05 - khz stopband sb 24.1 - - khz passband ripple pr - - 0.02 db stopband attenuation sa 54 - - db group delay ( note 26 ) gd - 20 - 1/fs dac digital filter (lpf) + scf: frequency response: 0 20.0khz fr - 1.0 - db note 25. the passband and stopband frequencies scale with fs (system sampling rate). for example, adc is pb = 20.0khz = 0.454*fs (@-1.0db). each response refers to that of 1khz. note 26. the calculation delay time caused by digital filtering. this time is from the input of analog signal to setting of the 16-bit data of both channels to the output register of the adc. this time includes the group delay of the hpf. for the dac, this time is from setting the 16-bit data of both channels from the input register to the output of analog signal. dc characteristics (ta = 25 c; avdd =2.2 3.6v, dvdd =1.6 3.6v, svdd =2.2 4.0v) parameter symbol min typ max units high-level input voltage (dvdd 2.2v) (dvdd < 2.2v) low-level input voltage (dvdd 2.2v) (dvdd < 2.2v) vih vil 70%dvdd 80%dvdd - - - - - - - - 30%dvdd 20%dvdd v v v v high-level output voltage (iout= ? 80 a) low-level output voltage (iout= 80 a) voh vol dvdd ? 0.4 - - - - 0.4 v v input leakage current iin - - 10 a
[ak4646] ms0557-e-05 2011/01 - 12 - switching characteristics (ta = 25 c; avdd =2.2 3.6v, dvdd =1.6 3.6v, svdd =2.2 4.0v; c l =20pf) parameter symbol min typ max units pll master mode (pll reference clock = mcki pin) mcki input timing frequency fclk 12 - 27 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns mcko output timing frequency fmck 0.2352 - 12.288 mhz duty cycle except 256fs at fs=32khz, 29.4khz dmck 40 50 60 % 256fs at fs=32khz, 29.4khz dmck - 33 - % lrck output timing frequency fs 7.35 - 48 khz duty cycle duty - 50 - % bick output timing period bcko bit = ? 0 ? tbck - 1/(32fs) - ns bcko bit = ? 1 ? tbck - 1/(64fs) - ns duty cycle dbck - 50 - % pll slave mode (pll reference clock = mcki pin) mcki input timing frequency fclk 12 - 27 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns mcko output timing frequency fmck 0.2352 - 12.288 mhz duty cycle except 256fs at fs=32khz, 29.4khz dmck 40 50 60 % 256fs at fs=32khz, 29.4khz dmck - 33 - % lrck input timing frequency fs 7.35 - 48 khz duty duty 45 - 55 % bick input timing period tbck 1/(64fs) - 1/(32fs) ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns
[ak4646] ms0557-e-05 2011/01 - 13 - parameter symbol min typ max units pll slave mode (pll reference clock = lrck pin) lrck input timing frequency fs 7.35 - 48 khz duty duty 45 - 55 % bick input timing period tbck 1/(64fs) - 1/(32fs) ns pulse width low tbckl 240 - - ns pulse width high tbckh 240 - - ns pll slave mode (pll reference clock = bick pin) lrck input timing frequency fs 7.35 - 48 khz duty duty 45 - 55 % bick input timing period pll3-0 bits = ? 0010 ? tbck - 1/(32fs) - ns pll3-0 bits = ? 0011 ? tbck - 1/(64fs) - ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns external slave mode mcki input timing frequency 256fs fclk 1.8816 - 12.288 mhz 512fs fclk 3.7632 - 13.312 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck input timing frequency 256fs fs 7.35 - 48 khz 512fs fs 7.35 - 26 khz 1024fs fs 7.35 - 13 khz duty duty 45 - 55 % bick input timing period tbck 312.5 - - ns pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns external master mode mcki input timing frequency 256fs fclk 1.8816 - 12.288 mhz 512fs fclk 3.7632 - 13.312 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck output timing frequency fs 7.35 - 48 khz duty cycle duty - 50 - % bick input timing period bcko bit = ? 0 ? tbck - 1/(32fs) - ns bcko bit = ? 1 ? tbck - 1/(64fs) - ns duty cycle dbck - 50 - %
[ak4646] ms0557-e-05 2011/01 - 14 - parameter symbol min typ max units audio interface timing master mode bick ? ? to lrck edge ( note 27 ) tmblr ? 40 - 40 ns lrck edge to sdto (msb) (except i 2 s mode) tlrd ? 70 - 70 ns bick ? ? to sdto tbsd ? 70 - 70 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns slave mode lrck edge to bick ? ? ( note 27 ) tlrb 50 - - ns bick ? ? to lrck edge ( note 27 ) tblr 50 - - ns lrck edge to sdto (msb) (except i 2 s mode) tlrd - - 80 ns bick ? ? to sdto tbsd - - 80 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns control interface timing cclk period tcck 200 - - ns cclk pulse width low tcckl 80 - - ns pulse width high tcckh 80 - - ns cdtio setup time tcds 40 - - ns cdtio hold time tcdh 40 - - ns csn ?h? time tcsw 150 - - ns csn edge to cclk ? ? ( note 28 ) tcss 50 - - ns cclk ? ? to csn edge ( note 28 ) tcsh 50 - - ns cclk ? ? to cdtio (at read command) tdcd - - 70 ns csn ? ? to cdtio (hi-z) (at read command) tccz - - 70 ns power-down & reset timing pdn pulse width ( note 29 ) tpd 150 - - ns pmadl or pmadr ? ? to sdto valid ( note 30 ) tpdv - 1059 - 1/fs note 27. bick rising edge must not occur at the same time as lrck edge. note 28. cclk rising edge must not occur at the same time as csn edge. note 29. the ak4646 can be reset by the pdn pin = ?l?. note 30. this is the count of lrck ? ? from the pmadl or pmadr bit = ?1?.
[ak4646] ms0557-e-05 2011/01 - 15 - timing diagram lrck 1/fclk mcki tclkh tclkl vih vil 1/fmck mcko tmckl 50%dvdd 1/fs tlrckh tlrckl 50%dvdd duty = tlrckh x fs x 100 tlrckl x fs x 100 dmck = tmckl x fmck x 100 note 31. mcko is not available at ext master mode. figure 2. clock timing (pll / ext master mode) lrck 50%dvdd bick 50%dvdd sdto 50%dvdd tbsd tsds sdti vil tsdh vih tblr tbckl tdlr figure 3. audio interface ti ming (pll/ext master mode)
[ak4646] ms0557-e-05 2011/01 - 16 - 1/fclk mcki tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil tlrckh tlrckl fmck mcko tmckl 50%dvdd dmck = tmckl x fmck x 100 duty = tlrckh x fs x 100 = tlrckl x fs x 100 figure 4. clock timing (pll slave mode; pll reference clock = mcki pin) 1/fclk mcki tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil tlrckh tlrckl duty = tlrckh x fs x 100 tlrckl x fs x 100 figure 5. clock timing (ext slave mode)
[ak4646] ms0557-e-05 2011/01 - 17 - lrck vih vil tblr bick vih vil tlrd sdto 50%dvdd tlrb tbsd tsds sdti vil tsdh vih msb figure 6. audio interface timing (pll/ext slave mode) csn vih vil tcss cclk tcds vih vil cdtio vih tcckh tcckl tcdh vil c1 c0 r/w tcck tcsh figure 7. write command input timing csn vih vil tcsh cclk vih vil cdtio vih tcsw vil d1 d0 d2 tcss figure 8. write data input timing
[ak4646] ms0557-e-05 2011/01 - 18 - csn cclk 50% dvdd cdtio vih d3 d2 d1 d0 tccz tdcd vil vih vil hi-z clock, h or l figure 9. read data output timing pmadl bit or pmadr bit tpdv sdto 50%dvdd figure 10. power down & reset timing 1 tpd pdn vil figure 11. power down & reset timing 2
[ak4646] ms0557-e-05 2011/01 - 19 - operation overview system clock there are the following five clock modes to interface with external devices ( table 1 and table 2 ). mode pmpll bit m/s bit pll3-0 bits figure pll master mode ( note 32 ) 1 1 table 4 figure 12 pll slave mode 1 (pll reference clock: mcki pin) 1 0 table 4 figure 13 pll slave mode 2 (pll reference clock: lrck or bick pin) 1 0 table 4 figure 14 figure 15 ext slave mode 0 0 x figure 16 ext master mode 0 1 x figure 17 note 32. if m/s bit = ?1?, pmpll bit = ?0? and mcko bit = ?1? during the setting of pll master mode, the invalid clocks are output from mcko pin when mcko bit is ?1?. table 1. clock mode setting (x: don?t care) mode mcko bit mcko pin mcki pin bick pin lrck pin 0 ?l? pll master mode 1 selected by ps1-0 bits selected by pll3-0 bits output (selected by bcko bit) output (1fs) 0 ?l? pll slave mode (pll reference clock: mcki pin) 1 selected by ps1-0 bits selected by pll3-0 bits input (selected by bcko bit) input (1fs) pll slave mode (pll reference clock: lrck or bick pin) 0 ?l? gnd input (selected by bcko bit) input (1fs) ext slave mode 0 ?l? selected by fs3-0 bits input ( 32fs) input (1fs) ext master mode 0 ?l? selected by fs1-0 bits output (selected by bcko bit) output (1fs) note 33. when pmvcm bit = m/s bit = ?1? and mcki is input, lrck and bick are output, even if pmdac bit = pmadl bit = pmadr bit = ?0?. table 2. clock pins state in clock mode master mode/slave mode the m/s bit selects either master or sl ave mode. m/s bit = ?1? selects master m ode and ?0? selects slave mode. when the ak4646 is power-down mode (pdn pin = ?l?) and exits reset st ate, the ak4646 is slave mode. after exiting reset state, the ak4646 goes to master mode by changing m/s bit = ?1?. when the ak4646 is on the master mode, lrck and bick pins are a floating state until m/s bit becomes ?1?. lrck and bick pins of the ak4646 should be pulled-down or pulled-up by the resistor (about 100k ) externally to avoid the floating state. m/s bit mode 0 slave mode (default) 1 master mode table 3. select master/slave mode
[ak4646] ms0557-e-05 2011/01 - 20 - pll mode when pmpll bit is ?1?, a fully integrated analog phase lock ed loop (pll) generates a clock that is selected by the pll3-0 and fs3-0 bits. the pll lock time is shown in table 4 , when the ak4646 is supplied stable clocks after pll is powered-up (pmpll bit = ?0? ?1?) or when the sampling frequency is changed. 1) setting of pll mode r and c of vcoc pin mode pll3 bit pll2 bit pll1 bit pll0 bit pll reference clock input pin input frequency r[ ] c[f] pll lock time (max) 0 0 0 0 0 lrck pin 1fs 6.8k 220n 160ms (default) 1 0 0 0 1 n/a - - - - 2 0 0 1 0 bick pin 32fs 10k 4.7n 2ms 10k 10n 4ms 3 0 0 1 1 bick pin 64fs 10k 4.7n 2ms 10k 10n 4ms 6 0 1 1 0 mcki pin 12mhz 10k 10n 40ms 7 0 1 1 1 mcki pin 24mhz 10k 10n 40ms 12 1 1 0 0 mcki pin 13.5mhz 10k 10n 40ms 13 1 1 0 1 mcki pin 27mhz 10k 10n 40ms others others n/a table 4. setting of pll mode (*fs: sampling frequency) 2) setting of sampling frequency in pll mode when pll2 bit is ?1? (pll reference clock input is mcki pin), the sampling frequency is selected by fs3-0 bits as defined in table 5 . mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency 0 0 0 0 0 8khz (default) 1 0 0 0 1 12khz 2 0 0 1 0 16khz 3 0 0 1 1 24khz 4 0 1 0 0 7.35khz 5 0 1 0 1 11.025khz 6 0 1 1 0 14.7khz 7 0 1 1 1 22.05khz 10 1 0 1 0 32khz 11 1 0 1 1 48khz 14 1 1 1 0 29.4khz 15 1 1 1 1 44.1khz others others n/a table 5. setting of sampling frequency at pll2 bit = ?1? and pmpll bit = ?1? (reference clock = mcki pin) when pll2 bit is ?0? (pll reference clock input is lrck or bick pin), the sampling frequency is selected by fs3 and fs2 bits. ( table 6 ). mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency range 0 0 0 don?t care don?t care 7.35khz fs 12khz (default) 1 0 1 don?t care don?t care 12khz < fs 24khz 2 1 0 don?t care don?t care 24khz < fs 48khz others others n/a table 6. setting of sampling frequency at pll2 bit = ?0? and pmpll bit = ?1? pll slave mode 2 (pll reference: clock: lrck or bick pin)
[ak4646] ms0557-e-05 2011/01 - 21 - pll unlock state 1) pll master mode (pmpll bit = ?1?, m/s bit = ?1?) in this mode, lrck and bick pins go to ?l? and irregul ar frequency clock is output from mcko pins at mcko bit is ?1? before the pll goes to lock state after pmpll bit = ?0? ? ?1?. if mcko bit is ?0?, mcko pin goes to ?l? ( table 7 ). after the pll is locked, a first period of lrck and bick may be invalid clock, but these clocks return to normal state after a period of 1/fs. when sampling frequency is changed, bick and lrck pins do not output irregular frequency clocks but go to ?l? by setting pmpll bit to ?0?. mcko pin pll state mcko bit = ?0? mcko bit = ?1? bick pin lrck pin after that pmpll bit ?0? ? ?1? ?l? output invalid ?l? output ?l? output pll unlock (except the case above) ?l? output invalid invalid invalid pll lock ?l? output table 9 table 10 1fs output table 7. clock operation at pll master mode (pmpll bit = ?1?, m/s bit = ?1?) 2) pll slave mode (pmpll b it = ?1?, m/s bit = ?0?) in this mode, an invalid clock is output from mcko pin before the pll goes to lock state after pmpll bit = ?0? ? ?1?. then, the clock selected by table 9 is output from mcko pin when pll is locked. adc and dac output invalid data when the pll is unlocked. for dac, the output signal should be muted by writing ?0? to dacl and dacs bits. mcko pin pll state mcko bit = ?0? mcko bit = ?1? after that pmpll bit ?0? ? ?1? ?l? output invalid pll unlock ?l? output invalid pll lock ?l? output output table 8. clock operation at pll slave mode (pmpll bit = ?0?, m/s bit = ?0?)
[ak4646] ms0557-e-05 2011/01 - 22 - pll master mode (pmpll bit = ?1?, m/s bit = ?1?) when an external clock (12mhz, 13.5mhz, 24mhz or 27mhz) is input to mcki pin, the mcko, bick and lrck clocks are generated by an internal pll circuit. the mcko output frequency is selected by ps1-0 bits ( table 9 ) and the output is enabled by mcko bit. the bick output frequency is selected between 32fs or 64fs, by bcko bit ( table 10 ). ak4646 dsp or p mcko bick lrck sdto sdti bclk lrck sdti sdto mcki 1fs 32fs, 64fs 256fs/128fs/64fs/32fs 12mhz, 13.5mhz, 24mhz, 27mhz mclk figure 12. pll master mode mode ps1 bit ps0 bit mcko pin 0 0 0 256fs (default) 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs table 9. mcko output frequency (pll mode, mcko bit = ?1?) bcko bit bick output frequency 0 32fs (default) 1 64fs table 10. bick output frequency at master mode
[ak4646] ms0557-e-05 2011/01 - 23 - pll slave mode (pmpll bit = ?1?, m/s bit = ?0?) a reference clock of pll is selected among the input clocks to mcki, bick or lrck pin. the required clock for the ak4646 is generated by an internal pll circuit. input frequency is selected by pll3-0 bits ( table 4 ). a) pll reference clock: mcki pin bick and lrck inputs should be synchronized with mcko output. the phase between mcko and lrck dose not matter. mcko pin outputs the frequency selected by ps1-0 bits ( table 9 ) and the output is enabled by mcko bit. sampling frequency can be selected by fs3-0 bits ( table 5 ). ak4646 dsp or p mcko bick lrck sdto sdti bclk lrck sdti sdto mcki 1fs 32fs 12mhz, 13.5mhz, 24mhz, 27mhz mclk 256fs/128fs/64fs/32fs figure 13. pll slave mode 1 (pll reference clock: mcki pin)
[ak4646] ms0557-e-05 2011/01 - 24 - b) pll reference clock: bick or lrck pin sampling frequency corresponds to 7.35khz to 48khz by changing fs3-0 bits ( table 6 ). a k4646 dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto mcko 1fs 32fs or 64fs figure 14. pll slave mode 2 (pll reference clock: lrck or bick pin) ak4646 dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto mcko 1fs 32fs figure 15 pll slave mode 2 (pll reference clock: lrck pin) the external clocks (mcki, bick and lrck) should always be present whenever the adc or dac is in operation (pmadl bit = ?1?, pmadr bit = ?1? or pmdac bit = ?1?). if these clocks are not provided, the ak4646 may draw excess current and it is not possible to ope rate properly because utilizes dynamic refre shed logic internally. if the external clocks are not present, the adc and dac should be in the power-down mode (pmadl=pmadr=pmdac bits = ?0?).
[ak4646] ms0557-e-05 2011/01 - 25 - ext slave mode (pmpll bit = ?0?, m/s bit = ?0?) when pmpll bit is ?0?, the ak4646 becomes ext mode. master clock can directly be inputted from mcki pin, without the internal pll circuit operation. this mode is compatible with i/f of the normal audio codec. the clocks required to operate this mode are mcki (256fs, 512fs or 1024fs), lrck (fs) and bick ( 32fs). the master clock (mcki) should be synchronized with lrck. the phase between these clocks does not matter. the input frequency of mcki is selected by fs1-0 bits ( table 11 ). mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 don?t care 0 0 256fs 7.35khz 48khz (default) 1 don?t care 0 1 1024fs 7.35khz 13khz 2 don?t care 1 0 512fs 7.35khz 26khz 3 don?t care 1 1 256fs 7.35khz 48khz others others n/a n/a table 11. mcki frequency at ext slave mode (pmpll bit = ?0?, m/s bit = ?0?) the s/n of the dac at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. the out-of-band noise can be improved by using higher freque ncy of the master clock. the s/n of the dac output through lout/rout pins at fs=8khz is shown in table 12 . mcki s/n (fs=8khz, 20khzlpf + a-weighted) 256fs 83db 512fs 93db 1024fs 93db table 12. relationship between mcki and s/n of lout/rout pins the external clocks (mcki, bick and lrck) should always be present whenever the adc or dac is in operation (pmadl bit = ?1?, pmadr bit = ?1? or pmdac bit = ?1?). if these clocks are not provided, the ak4646 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. when the external clocks are not present, the adc and dac shoul d be in the power-down mode (pmadl=pmadr=pmdac bits = ?0?). ak4646 dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto mcko 1fs 32fs mclk 256fs, 512fs or 1024fs figure 16. ext slave mode
[ak4646] ms0557-e-05 2011/01 - 26 - ext master mode (pmpll bit = ?0?, m/s bit = ?1?) the ak4646 becomes ext master mode by setting pmpll bit = ?0? and m/s bit = ?1?. master clock is input from mcki pin, the internal pll circuit is not operated. the clock required to operate is mcki (256fs, 512fs or 1024fs). the input frequency of mcki is selected by fs1-0 bits ( table 13 ). mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 don?t care 0 0 256fs 7.35khz 48khz (default) 1 don?t care 0 1 1024fs 7.35khz 13khz 2 don?t care 1 0 256fs 7.35khz 48khz 3 don?t care 1 1 512fs 7.35khz 26khz table 13. mcki frequency at ext master mode (pmpll bit = ?0?, m/s bit = ?1?) the s/n of the dac at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. the out-of-band noise can be improved by using higher freque ncy of the master clock. the s/n of the dac output through lout/rout pins at fs=8khz is shown in table 14 . mcki s/n (fs=8khz, 20khzlpf + a-weighted) 256fs 83db 512fs 93db 1024fs 93db table 14. relationship between mcki and s/n of lout/rout pins mcki should always be present whenever the adc or dac is in operation (pmadl bit = ?1?, pmadr bit = ?1? or pmdac bit = ?1?). if mcki is not provided, the ak4646 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. if mcki is not pres ent, the adc and dac should be in the power-down mode (pmadl=pmadr=pmdac bits = ?0?). ak4646 dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto mcko 1fs 32fs or 64fs mclk 256fs, 512fs or 1024fs figure 17. ext master mode bcko bit bick output frequency 0 32fs (default) 1 64fs table 15. bick output frequency at master mode
[ak4646] ms0557-e-05 2011/01 - 27 - system reset upon power-up, the pdn pin should be ?l? and be changed from ?l? to ?h? after all power supply are supplied. ?l? time of 150ns or more is needed to reset in the ak4646. this ensu res that all internal register s reset to their initial values. the adc enters an initialization cycle that starts when the pmadl or pmadr bit is changed from ?0? to ?1?. the initialization cycle time is 1059/fs=24ms@fs =44.1khz. during the initialization cycl e, the adc digital data outputs of both channels are forced to a 2's comp liment, ?0?. the adc output reflects the analog input signal after the initialization cycle is complete. the dac outputs unexpected data after pmdac bit ?0? ?1? until 67/fs = 1.52ms@fs = 44.1khz, then the dac starts outputting the normal voltage. (note) the initial data of adc has the offset data that depends on the condition of the microphone and the cut-off frequency of hpf. if this offset isn?t small, don?t use the initial data of adc. audio interface format three types of data formats are available and selected by setting the dif1-0 bits ( table 16 ). in all modes, the serial data is msb first, 2?s complement format. audio interface formats can be used in both master and slave modes. lrck and bick are output from the ak4646 in master mode, but must be input to the ak4646 in slave mode. the sdto is clocked out on the falling edge (? p ?) of bick and the sdti is latched on the rising edge (? n ?). mode dif1 bit dif0 bit sdto (adc) sdti (dac) bick figure 0 0 0 n/a n/a n/a - 1 0 1 msb justified lsb justified t 32fs figure 18 2 1 0 msb justified msb justified t 32fs figure 19 (default) 3 1 1 i 2 s compatible i 2 s compatible t 32fs figure 20 table 16. audio interface format if 16-bit data that adc outputs is converted to 8-bit data by removing lsb 8-bit, ? 1? at 16bit data is converted to ? 1? at 8-bit data. and when the dac playbacks this 8-bit data, ? 1? at 8-bit data will be converted to ? 256? at 16-bit data which is a large offset. this offset can be removed by adding the offset of ?128? to 16-bit data before converting to 8-bit data.
[ak4646] ms0557-e-05 2011/01 - 28 - lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 110 13 13 23 7 76543 210 6543 10 2 9 1112131415 0 12 3 15 14 13 1 0 15 15 76543 210 10 9 1112131415 bick(64fs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 13 don't care 10 1 15 15 210 15 0 15 14 15 14 don't care 15:msb, 0:lsb lch data rch data 15 14 13 76543 10 2 15 14 13 10 figure 18. mode 1 timing lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 110 13 13 23 7 76543 210 6543 10 2 9 1112131415 0 12 3 15 14 13 1 0 15 15 76543 210 10 9 1112131415 bick(64fs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 13 don't care 1 15 15 15 0 15 14 15 14 don't care 15:msb, 0:lsb lch data rch data 13 10 13 10 15 15 14 13 76543 10 2 15 14 13 10 figure 19. mode 2 timing
[ak4646] ms0557-e-05 2011/01 - 29 - lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 110 23 7 76543 210 6543 10 2 9 1112131415 0 12 3 15 14 1 0 76543 210 10 9 1112131415 bick(64fs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 don't care 2 15 1 15 15 15 don't care 15:msb, 0:lsb lch data rch data 14 21 14 21 8 8 8 0 0 0 0 0 15 14 76543 210 8 15 14 21 0 figure 20. mode 3 timing mono/stereo mode pmadl and pmadr bits set mono/stereo adc operation. when changing adc operation, pmadl and pmadr bits should be set ?0? at first. pmadl bit pmadr bit adc lch data adc rch data 0 0 all ?0? all ?0? (default) 0 1 rch input signal rch input signal 1 0 lch input signal lch input signal 1 1 lch input signal rch input signal table 17. mono/stereo adc operation
[ak4646] ms0557-e-05 2011/01 - 30 - mic/line input selector the ak4646 has an input selector. when mdif1 and mdif2 bits are ?0?, inl and inr bits select lin1/lin2 and rin1/rin2, respectively. when mdif1 and mdif2 bits ar e ?1?, lin1, rin1, lin2 and rin2 pins become in1 ? , in1+, in2+ and in2 ? pins respectively. in this case, full-differential input is available ( figure 22 ). mdif1 bit mdif2 bit inl bit inr bit lch rch 0 lin1 rin1 (default) 0 1 lin1 rin2 0 lin2 rin1 0 1 1 lin2 rin2 0 x lin1( note 34 ) in2+/ ? 0 1 1 x n/a n/a 0 n/a n/a 0 x 1 in1+/ ? rin2( note 35 ) 1 1 x x in1+/ ? in2+/ ? note 34. any signal should be input to rin1 pin, when mdif1 bit = ?0?, mdif2 bit = ?1? and inl bit = ?0?. note 35. any signal should be input to lin2 pin, when mdif1 bit = ?1?, mdif2 bit = ?0? and inl bit = ?1?. table 18. mic/line in path select lin1/in1 ? pin a dc lch rin1/in1+ pin inl bit mdif1 bit rin2/in2 ? pin a dc rch lin2/in2+ pin inr bit mdif2 bit ak4646 figure 21. mic/line input selector inx ? pin inx+ pin mpwr pin a k4646 mic-amp 1k 1k r1 r2 figure 22. connection example for full-differe ntial mic input (mdif1/2 bits = ?1?)
[ak4646] ms0557-e-05 2011/01 - 31 - mic gain amplifier the ak4646 has a gain amplifier for microphone input. the gain of mic-amp is selected by the mgain2-0 bits ( table 19 ). the typical input impedance is 30k (typ). mgain2 bit mgain1 bit mgain0 bit input gain 0 0 0 0db 0 0 1 +20db (default) 0 1 0 +26db 0 1 1 +32db 1 0 0 +10db 1 0 1 +17db 1 1 0 +23db 1 1 1 +29db table 19. mic input gain mic power when pmmp bit = ?1?, the mpwr pin supplies power for the microphone. this output voltage is typically 0.8 x avdd and the load resistance is minimum 0.5k . in case of using two sets of stereo microphone, the load resistance is minimum 2k for each channel. any capacitor must not be connected directly to mpwr pin ( figure 23 ). pmmp bit mpwr pin 0 hi-z (default) 1 output table 20. mic power mpwr pin figure 23. mic block circuit
[ak4646] ms0557-e-05 2011/01 - 32 - digital block the digital block consists of block diagram as shown in figure 24 . hpf ~ alc blocks are used for recording path when dafil bit = ?0? and either adc (lch or rch) is powered-up. also hpf ~ alc bloc ks are used for playback path when dafil bit = ?1? or both adc (lch and rch) are powered-down ( figure 24 ~ figure 27 , table 21 ). the sdto pin outputs ?l? when dafil bit = ?1?, even if adc is powered-up. dac 1st order hpf adc alc (volume) datt smute sdti sw1 ?1? ?0? 1st order hpf sw2 ?1? ?0? sdto hpf bit hpfad bit pmadl bit pmadr bit pmdac bit dafil bit pmdac bit pmadcl/r bit 1st order lpf lpf bit stereo separation fil3 bit gain compensation eq0 bit gn1-0 bits 5 band eq eq5-1 bit a lc1/2 bits digital programmable filter block sw1, sw2: see table 21 (1) adc: include the digital filter (lpf) for adc as shown in ?filter chracteristics?. (2) dac: include the digital filter (lpf) for dac as shown in ?filter chracteristics?. (3) hpf: high pass filter. applicable to use as wind- noise reduction filter. (see ?programmable filter?) (4) lpf: low pass filter (see ?digital programmable filter?.) (5) stereo separation: digital se paration emphasis filter (see ?digital programmable filter?) (6) gain compensation: composed of the equalizer (e q0) and the gain (0bb/+12db/+24db). compensate the frequency response and the gain after th e stereo separation emphasis filter. (7) 5-band notch: applicable to use as equalizer or notch filter. (see ?digital programmable filter?) (8) alc: input digital volume with alc functi on. (see ?input digital volume? and ?alc?) (9) datt: 4-band digital volume for reco rding path. (see ?digital volume 2?) (10) smute: soft mute. (see ?soft mute?.) figure 24 digital block path select
[ak4646] ms0557-e-05 2011/01 - 33 - pmadl pmadr pmdac dafil loop figure 24 sw mode bit bit bit bit bit sw1 sw2 figure recording mode 1 1 x 0 0 1 0 figure 25 1 0 x 0 0 1 0 0 1 x 0 0 1 0 playback mode 0 0 1 0 0 0 1 figure 26 x x 1 1 0 0 1 loop through 1 1 1 0 1 1 1 figure 27 mode 1 0 1 0 1 1 1 0 1 1 0 1 1 1 (x: don?t care) table 21. recordi ng playback mode lpf bit, hpf bit, fil3 bit, eq 0 bit, eq1 bit, eq2 bit, eq3 bit, eq4 bit, eq5 bit, acl1 bit and alc2 bit should be ?0? when selecting those modes. dac 2nd order hpf adc 5 band eq alc (volume) datt smute 1st order lpf stereo separation gain compensation figure 25. path at recording mode (default) dac 1st order hpf adc 5 band eq alc (volume) datt smute 1st order lpf stereo separation gain compensation 1st order hpf ?0? data figure 26. path at playback mode dac 2nd order hpf adc 5 band eq alc (volume) datt smute 1st order lpf stereo separation gain compensation figure 27. path at loop through mode
[ak4646] ms0557-e-05 2011/01 - 34 - digital programmable filter circuit (1) high pass filter (hpf) normally, this hpf is used for a wind-noise reduction filter. this is composed with 2 steps of 1st order hpf. the coefficient of both hpf is the same and set by f1a13-0 b its and f1b13-0 bits. hpfad bit controls on/off of the 1st step hpf and hpf bit controls on/off of the 2nd step hpf. wh en the hpf is off, the audio data passes this block by 0db gain. the coefficient should be set when hpfad= hpf bits = ?0? or pmadl=pmadr= pmdac bits = ?0?. fs: sampling frequency fc: cut-off frequency register setting ( note 36 ) hpf: f1a[13:0] bits =a, f1b[13:0] bits =b (msb=f1a13, f1b13; lsb=f1a0, f1b0) a = 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function h(z) = a 1 ? z ? 1 1 + bz ? 1 the cut-off frequency should be set as below. fc/fs 0.0001 (fc min = 4.41hz at 44.1khz) (2) low pass filter (lpf) this is composed with 1st order lpf. f2a13-0 bits and f2b 13-0 bits set the coefficient of lpf. lpf bit controls on/off of the lpf. when the lpf is off, the audio data passes this block by 0db gain. the coeffi cient should be set when lpf bit = ?0? or pmadl=pmadr=pmdal=pmdar bits = ?0?. fs: sampling frequency fc: cut-off frequency register setting ( note 36 ) lpf: f2a[13:0] bits =a, f2b[13:0] bits =b (msb=f2a13, f1b13; lsb=f2a0, f2b0) a = 1 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function h(z) = a 1 + z ? 1 1 + bz ? 1 the cut-off frequency should be set as below. fc/fs 0.05 (fc min = 2205hz at 44.1khz)
[ak4646] ms0557-e-05 2011/01 - 35 - (3) stereo separation emphasis filter (fil3) fil3 is used to emphasize the stereo sepa ration of stereo mic recording data or playback data. f3a13-0 and f3b13-0 bits set the filter coefficient of fil3. fil3 becomes high pass filter (hpf) at f3as bit = ?0?, and low pass filter (lpf) at f3as bit = ?1?. fil3 bit controls on/ off of fil3. when stereo separation em phasis filter is off, the audio data passes this block by 0db gain. the coe fficient should be set when fil3 bit = ?0? or pmadl = pmadr = pmdac bits = ?0?. 1) when fil3 is set to ?hpf? fs: sampling frequency fc: cut-off frequency k: filter gain [db] (0db k ? 10db) register setting ( note 36 ) fil3: f3as bit = ?0?, f3a[13:0] bits =a, f3b[13:0] bits =b (msb=f3a13, f3b13; lsb=f3a0, f3b0) a = 10 k/20 x 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function h(z) = a 1 ? z ? 1 1 + bz ? 1 2) when fil3 is set to ?lpf? fs: sampling frequency fc: cut-off frequency k: filter gain [db] (0db k ? 10db) register setting ( note 36 ) fil3: f3as bit = ?1?, f3a [13:0] bits =a, f3b [13:0] bits =b (msb=f3a13, f3b13; lsb= f3a0, f3b0) a = 10 k/20 x 1 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function h(z) = a 1 + z ? 1 1 + bz ? 1
[ak4646] ms0557-e-05 2011/01 - 36 - (4) gain compensation (eq0) gain compensation is used to compensate the frequency res ponse and the gain that is ch anged by stereo separation emphasis filter. gain compensation is composed of the equalizer (eq0) and the gain (0db/+12db/+24db). e0a15-0, e0b13-0 and e0c15-0 bits set the coeffici ent of eq0. gn1-0 bits set the gain ( table 22 ). eq0 bit controls on/off of eq0. when eq is off and the gain is 0db, the audio data passes this block by 0db gain. the coefficient should be set when eq0 bit = ?0? or pmadl =pmadr= pmdac bits = ?0?. fs: sampling frequency fc 1 : pole frequency fc 2 : zero-point frequency k: filter gain [db] (maximum +12db) register setting ( note 36 ) e0a[15:0] bits =a, e0b[13:0] bits =b, e0c[15:0] bits =c (msb=e0a15, e0b13, e0c15; lsb=e0a0, e0b0, e0c0) a = 10 k/20 x 1 + 1 / tan ( fc 2 /fs) 1 + 1 / tan ( fc 1 /fs) b = 1 ? 1 / tan ( fc 1 /fs) 1 + 1 / tan ( fc 1 /fs) , c =10 k/20 x 1 ? 1 / tan ( fc 2 /fs) 1 + 1 / tan ( fc 1 /fs) , transfer function h(z) = a + cz ? 1 1 + bz ? 1 gain[db] k fc 1 fc 2 frequency figure 28. eq0 frequency response gn1 gn0 gain 0 0 0db (default) 0 1 +12db 1 x +24db table 22. gain select of gain block (x: don?t care)
[ak4646] ms0557-e-05 2011/01 - 37 - (5) 5-band notch this block can be used as equalizer or notch filter. 5- band equalizer (eq1, eq2, eq3, eq4 and eq5) is selected on/off independently by eq1, eq2, eq3, eq4 and eq5 bits. when equalizer is off, the audio data passes this block by 0db gain. e1a15-0, e1b15-0 and e1c15-0 bits set the co efficient of eq1. e2a15-0, e2b15-0 and e2c15-0 bits set the coefficient of eq2. e3a15-0, e3b15-0 and e3c15-0 bits set the coefficient of eq3. e4a15-0, e4b15-0 and e4c15-0 bits set the coefficient of eq4. e5a15-0, e5b15-0 and e5c15-0 bits set the coeffi cient of eq5. the eqx (x=1 5) coefficient should be set when eqx bit = ? 0 ? or pmadl=pmadr= pmdac bits = ?0?. fs: sampling frequency fo 1 ~ fo 5 : center frequency fb 1 ~ fb 5 : band width where the gain is 3db different from center frequency k 1 ~ k 5 : gain ( ? 1 k n 3) register setting ( note 36 ) eq1: e1a[15:0] bits =a 1 , e1b[15:0] bits =b 1 , e1c[15:0] bits =c 1 eq2: e2a[15:0] bits =a 2 , e2b[15:0] bits =b 2 , e2c[15:0] bits =c 2 eq3: e3a[15:0] bits =a 3 , e3b[15:0] bits =b 3 , e3c[15:0] bits =c 3 eq4: e4a[15:0] bits =a 4 , e4b[15:0] bits =b 4 , e4c[15:0] bits =c 4 eq5: e5a[15:0] bits =a 5 , e5b[15:0] bits =b 5 , e5c[15:0] bits =c 5 (msb=e1a15, e1b15, e1c15, e2a15, e2b15, e2c15, e3a15, e3b15, e3c15, e4a15, e4b15, e4c15, e5a15, e5b15, e5c15; lsb= e1a0, e1b0, e1c0, e2a0, e2b0, e2c0, e3a0, e3b0, e3c0, e4a0, e4b0, e4c0, e5a0, e5b0, e5c0) a n = k n x tan ( fb n /fs) 1 + tan ( fb n /fs) b n = cos(2 fo n /fs) x 2 1 + tan ( fb n /fs) , c n = 1 ? tan ( fb n /fs) 1 + tan ( fb n /fs) , (n = 1, 2, 3, 4, 5) transfer function h n (z) = a n 1 ? z ? 2 1 ? b n z ? 1 ? c n z ? 2 h(z) = 1 + h 1 (z) + h 2 (z) + h 3 (z) + h 4 (z) + h 5 (z) (n = 1, 2, 3, 4, 5) the center frequency should be set as below. fo n / fs < 0.497 when gain of k is set to ?-1?, the equali zer becomes notch filter. when it is used as notch filter, central frequency of a real notch filter deviates from the above-mentioned calculation, if its central frequency of each band is near. the control soft that is attached to the evaluation board has functions that revise a gap of frequency and calculate the coefficient. when its central frequency of each band is near, the central frequenc y should be revised and conf irm the frequency response. note 36. [translation the filter coeffici ent calculated by the equations above fro m real number to binary code (2?s complement)] x = (real number of filter coefficient calculated by the equations above) x 2 13 x should be rounded to integer, a nd then should be translated to binary code (2?s complement). msb of each filter coefficient setting register is sine bit.
[ak4646] ms0557-e-05 2011/01 - 38 - alc operation the alc (automatic level control) is operated by alc block when alc bit is ?1?. when both lch and rch of adc are powered-down or dafil bit is ?1?, alc circuit operates at playback path. when either lch and rch of adc is powered-up and dafil bit is ?0?, alc circuit operates at recording path. note 37. in this section, vol means ivl and ivr fo r recording path, ovl and ovr for playback path. note 38. in this section, alc bit means alc1 b it for recording path, alc2 bit for playback path. note 39. in this section, ref means iref fo r recording path, oref for playback path. 1. alc limiter operation during the alc limiter operation, when either lch or rch exceeds the alc limiter detection level ( table 23 ), the vol value (same value for both l and r) is attenuated automati cally by the amount defined by the alc limiter att step ( table 24 ). the vol is then set to the same value for both channels. when zelmn bit = ?0? (zero cross detec tion is enabled), the vol value is ch anged by alc limiter operation at the individual zero crossing points of lch and rch or at the zero crossing timeout. ztm 1-0 bits set the zero crossing timeout period of both alc limiter and recovery operation ( table 25 ). in addition, when lfst bit = ?1?, in the case of a output level exceeding fs, it is changed in 1step (l/r common) instan tly (cycle: 1/fs). in the cas e of an output level does not exceeding fs, it is zero crossing or vol value is ch anged at the time of being zero crossing timeout. when zelmn bit = ?1? (zero cross detecti on is disabled), vol value is immedi ately (period: 1/fs) changed by alc limiter operation. attenuation step is fixed to 1 step regardless as the setting of lmat1-0 bits. the attenuation operation is done continuously until the i nput signal level becomes alc limiter detection level ( table 23 ) or less. after completing the attenuation ope ration, unless alc bit is changed to ?0 ?, the operation repeats when the input signal level exceeds lmth1-0 bits. lmth1 lmth0 alc limiter detection level al c recovery waiting counter reset level 0 0 alc output ? 2.5dbfs ? 2.5dbfs > alc output ? 4.1dbfs (default) 0 1 alc output ? 4.1dbfs ? 4.1dbfs > alc output ? 6.0dbfs 1 0 alc output ? 6.0dbfs ? 6.0dbfs > alc output ? 8.5dbfs 1 1 alc output ? 8.5dbfs ? 8.5dbfs > alc output ? 12dbfs table 23. alc limiter detection level / recovery counter reset level alc1 limiter att step lmat1 lmat0 alc1 output lmth alc1 output fs alc1 output fs + 6db alc1 output fs + 12db 0 0 1 1 1 1 (default) 0 1 2 2 2 2 1 0 2 4 4 8 1 1 1 2 4 8 table 24. alc limiter att step (x: don?t care) zero crossing timeout period ztm1 ztm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms (default) 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 25. alc zero crossing timeout period
[ak4646] ms0557-e-05 2011/01 - 39 - 2. alc recovery operation the alc recovery operation waits for the wtm2-0 bits ( table 26 ) to be set after completing the alc limiter operation. if the input signal does not exceed ?alc r ecovery waiting counter reset level? ( table 23 ) during the wait time, the alc recovery operation is done. the vol value is au tomatically incremented by rgain1-0 bits ( table 27 ) up to the set reference level ( table 28 ) with zero crossing detection which tim eout period is set by ztm1-0 bits ( table 25 ). then the ivl and ivr are set to the same value for both channels. th e alc recovery operation is done at a period set by wtm2-0 bits. when zero cross is detected at both channels during th e wait period set by wtm2-0 bits, the alc recovery operation waits until wtm2-0 period and the next recovery operation is done. for example, when the current vol value is 30h and rgain1-0 bits are set to ?01?, vol is changed to 32h by the auto limiter operation and then the input signal level is gained by 0.75db (=0.375db x 2). when the vol value exceeds the reference level (ref7-0), the vol values are not increased. when ?alc recovery waiting counter reset level (lmth1-0) output signal < alc limiter detection level (lmth1-0)? during the alc recovery operation, the waiting timer of alc recovery operation is reset. when ?alc recovery waiting counter reset level (lmth1-0) > output signal?, the waiting timer of alc recovery operation starts. the alc operation corresponds to the impulse noise. if an impulse noise is input wh en fr bit = ?0?, the alc recovery operation becomes faster than a normal r ecovery operation. when large noise is input to microphone instantaneously, the quality of small level in the large noise can be improved by this fast recovery operation. the speed of fast recovery operation is set by rfst1-0 bits ( table 30 ). when fr bit = ?1?, this fast recove ry operation is not executed even if an impulse noise is input. alc recovery operation waiting period wtm2 wtm1 wtm0 8khz 16khz 44.1khz 0 0 0 128/fs 16ms 8ms 2.9ms (default) 0 0 1 256/fs 32ms 16ms 5.8ms 0 1 0 512/fs 64ms 32ms 11.6ms 0 1 1 1024/fs 128ms 64ms 23.2ms 1 0 0 2048/fs 256ms 128ms 46.4ms 1 0 1 4096/fs 512ms 256ms 92.9ms 1 1 0 8192/fs 1024ms 512ms 185.8ms 1 1 1 16384/fs 2048ms 1024ms 371.5ms table 26. alc recovery operation waiting period rgain1 rgain0 gain step 0 0 1 step 0.375db (default) 0 1 2 step 0.750db 1 0 3 step 1.125db 1 1 4 step 1.500db table 27. alc recovery gain step
[ak4646] ms0557-e-05 2011/01 - 40 - iref7-0bits gain(0db) step f1h +36.0 f0h +35.625 efh +35.25 : : e1h +30.0 (default) : : 92h +0.375 91h 0.0 90h -0.375 : : 0.375db 2h -53.625 1h -54.0 0h mute table 28. reference level at alc recovery operation for recoding oref5-0bits gain(0db) step 3ch +36.0 3bh +34.5 3ah +33.0 : : 28h +6.0 (default) : : 25h +1.5 24h 0.0 23h -1.5 : : 1.5db 2h -51.0 1h -52.5 0h -54.0 table 29. reference level at alc recovery operation for playback rfst1 bit rfst0 bit recovery speed 0 0 quad speed (default) 0 1 8times 1 0 16times 1 1 n/a table 30. fast recovery speed setting (fr bit = ?0?)
[ak4646] ms0557-e-05 2011/01 - 41 - 3. the volume at the alc operation the current volume value at the alc operati on is reflected by vol7-0 bits. it is en able to check the current volume value with reading the register value of vol7-0 bits. vol7-0bits gain(0db) f1h +36.0 f0h +35.625 efh +35.25 : : c5h +19.5 : : 92h +0.375 91h 0.0 90h -0.375 : : 2h -53.625 1h -54.0 0h mute table 31. value of vol7-0 bits 4. example of alc operation table 32 and table 33 show the examples of the alc setting for recording and playback path. fs=8khz fs=44.1khz register name comment data operation data operation lmth1-0 limiter detection level 01 ? 4.1dbfs 01 ? 4.1dbfs zelmn limiter zero crossing det ection 0 enable 0 enable ztm1-0 zero crossing timeout period 01 32ms 11 23.2ms wtm2-0 recovery waiting period *wtm2-0 bits should be the same data as ztm1-0 bits 001 32ms 100 46.4ms iref7-0 maximum gain at recove ry operation e1h +30db e1h +30db ivl7-0, ivr7-0 gain of ivol e1h +30db e1h +30db lmat1-0 limiter att step 00 1 step 00 1 step lfst fast limiter operation 1 on 1 on rgain1-0 recovery gain step 00 1 step 00 1 step rfst1-0 fast recovery speed 00 4 times 00 4 times alc1 alc enable 1 enable 1 enable table 32. example of the alc setting (recording)
[ak4646] ms0557-e-05 2011/01 - 42 - fs=8khz fs=44.1khz register name comment data operation data operation lmth1-0 limiter detection level 01 ? 4.1dbfs 01 ? 4.1dbfs zelmn limiter zero crossing det ection 0 enable 0 enable ztm1-0 zero crossing timeout period 01 32ms 11 23.2ms wtm2-0 recovery waiting period *wtm2-0 bits should be the same data as ztm1-0 bits 001 32ms 100 46.4ms oref5-0 maximum gain at recove ry operation 28h +6db 28h +6db ovl7-0, ovr7-0 gain of vol 91h 0db 91h 0db lmat1-0 limiter att step 00 1 step 00 1 step lfst fast limiter operation 1 on 1 on rgain1-0 recovery gain step 00 1 step 00 1 step rfst1-0 fast recovery speed 00 4 times 00 4 times alc2 alc enable 1 enable 1 enable table 33. example of the alc setting (playback) the following registers should not be ch anged during the alc operation. these b its should be changed after the alc operation is finished by alc bit = ?0? or pmadl=pmadr bits = ?0?. ? lmth1-0, lmat1-0, wtm2-0, ztm1-0, rg ain1-0, ref7-0, zelmn, rfst1-0, lfst manual mode * the value of ivol should be the same or smaller than ref?s wr (ztm1-0, wtm2-0, rfst1-0) wr (iref7-0) wr (ivl/r7-0) wr (lmat1-0, rgain0, zelmn, lmth0; alc= ?1?) example: limiter = zero crossing enable recovery cycle = 32ms@8khz limiter and recovery step = 1 maximum gain = +30.0db limiter detection level = ? 4.1dbfs alc bit = ?1? (1) addr=06h, data=14h (2) addr=08h, data=e1h (5) addr=07h, data=21h (3) addr=09h&0ch, data=e1h alc operation wr (rgain1, lmth1) (4) addr=0bh, data=28h note : wr : write figure 29. registers set-up sequence at alc operation
[ak4646] ms0557-e-05 2011/01 - 43 - input digital volume (manual mode) the input digital volume becomes a manual mode at alc1 b it = ?0? when either lch and rch of adc is powered-up (pmadl bit = ?1? or pmadr bit = ?1?) and dafil bit is ?0?. this mode is used in the case shown below. 1. after exiting reset state, set-up the registers for the alc operation (ztm 1-0, lmth and etc) 2. when the registers for the alc operation (limiter period, recovery period and etc) are changed. for example; when the change of the sampling frequency. 3. when ivol is used as a manual volume. ivl7-0 and ivr7-0 bits set the gain of the volume control ( table 34 ). the ivol value is changed at zero crossing or timeout. the zero crossing timeout peri od is set by ztm1-0 bits. if ivl7-0 or ivr7-0 bits are written during pmadl=pmadr bits = ?0?, ivol operati on starts with the written values at the end of the adc initialization cycle after pmadl or pmadr b it is changed to ?1?. if ivl7-0 or ivr7-0 bits are written dur ing pmadl=pmadr bits = ?0?, ivol ope ration starts with the written values at the end of the adc initialization cycle afte r pmadl or pmadr bit is changed to ?1?. ivl7-0 ivr7-0 gain (db) step f1h +36.0 f0h +35.625 efh +35.25 : : e2h +30.375 e1h +30.0 (default) e0h +29.625 : : 03h ? 53.25 02h ? 53.625 01h ? 54 0.375db 00h mute table 34. input digital volume setting
[ak4646] ms0557-e-05 2011/01 - 44 - output digital volume (manual mode) the alc block becomes output digital vol ume (manual mode) by setting alc2 bit to ?0? when both lch and rch of adc are powered-down (pmadl = pmadr bits = ?1?) or dafil bit is ?1?. the output digital volume gain is set by the ovl7-0 bit and the ovr7-0 bit ( table 35 ). when the ovolc bit = ?1?, the ovl7-0 bits control both lch and rch volume levels. when the ovolc bit = ?0?, the ovl7-0 bits c ontrol lch level and the ovr7-0 bits control rch level. the ovol value is changed at zero crossing or timeout. th e zero crossing timeout period is set by ztm1-0 bits. ovl7-0 bits ovr7-0 bits gain(0db) step f1h +36.0 f0h +35.625 efh +35.25 : : 92h +0.375 91h 0.0 (default) 90h -0.375 : : 0.375db 2h -53.625 1h -54.0 0h mute table 35. output digital volume setting when writing to the ovl7-0 bits and ovr7-0 bit continuously, th e control register should be written by an interval more than zero crossing timeout. if not, the zero crossing counter is reset at each time and the volume will not be changed. however, it could be ignored when writing th e same register value as the last time. in this case, zero crossing counter will not be reset, so that it coul d be written by an interval less than zero crossing timeout. output digital volume 2 ak4646 has 4 steps output volume in add ition to the volume setting by datt1-0 bits. lch and rch have the same volume values, which are set by datt1-0 bits as shown in table 36 . datt1-0bits gain(0db) step 0h 0.0 (default) 1h -6.0 2h -12.0 6.0db 3h -18.1 table 36. output digital volume2 setting
[ak4646] ms0557-e-05 2011/01 - 45 - de-emphasis filter the ak4646 includes the digital de-emphasis filter (tc = 50/15 s) which corresponds 3 kinds frequency (32khz, 44khz, 48khz) by iir filter. setting the dem1-0 bits enables the de-emphasis filter ( table 37 ). dem1 dem0 mode 0 0 44.1khz 0 1 off (default) 1 0 48khz 1 1 32khz table 37. de-emphasis control soft mute soft mute operation is performed in the dig ital input domain. when the smute bit goes to ? 1 ? , the input signal is attenuated by ? ( ? 0 ? ) during the cycle of 256/fs (5.8msec@fs=44.1kh z). when the smute bit is returned to ? 0 ? , the mute is cancelled and the input attenuation gradually cha nges to 0db during the cycle of 256/fs (5.8msec@fs=44.1khz). if the soft mute is cancelled within the cycle of 256/fs (5.8msec@fs=44.1khz), the atte nuation is discontinued and returned to 0db. the soft mute for playback operation is effective for changing the si gnal source without stopping the signal transmission. smute bit a ttenuation 256/fs 0db - 256/fs gd gd (1) (2) (3) a nalog output figure 30. soft mute function (1) the input signal is attenuated by ? ( ? 0 ? ) during the cycle of 256/fs (5.8msec@fs=44.1khz). (2) analog output corresponding to digita l input has the group delay (gd). (3) if the soft mute is cancelled within the cycle of 256/ fs (5.8msec@fs=44.1khz), the a ttenuation is discounted and returned to 0db within the same cycle.
[ak4646] ms0557-e-05 2011/01 - 46 - analog mixing: mono input when the pmbp bit is set to ?1?, the mono input is powered-up. when the beeps bit is set to ?1?, the input signal from the min pin is output to speaker-amp. when the beeph bit is set to ?1?, the input signal from the min pin is output to headphone-amp. when the beepl bit is set to ?1?, the input signal from the min pin is output to the stereo line output amplifier. the external resister ri adjusts the signal level of min input. table 38 , and table 39 show the typical gain example at r i = 20k this gain is in inverse proportion to r i . min ri lout/rout pin beepl spp/spn pin beeps figure 7. block diagram of min pin lovl1-0 bits min ? lout/rout 00 0db (default) 01 +2db 10 +4db 11 +6db table 38. min input ? lout/rout output gain (typ) at r i = 20k min ? spp/spn spkg1-0 bits alc2 bit = ? 0 ? alc2 bit = ? 1 ? 00 +4.6db +6.6db (default) 01 +6.6db +8.6db 10 +8.6db +10.6db 11 +10.6db +12.6db table 39. min input ? speaker-amp output gain (typ) at r i = 20k
[ak4646] ms0557-e-05 2011/01 - 47 - stereo line output (lout/rout pins) when dacl bit is ?1?, lch/rch signal of dac is output from the lout/rout pins which is single-ended. when dacl bit is ?0?, output signal is muted and lout/rout pins output vcom voltage. the load impedance is 10k (min.). when the pmlo bit = lops bit = ?0?, the stereo line output enters power-down mode and the output is pulled-down to avss by 100k (typ). when the lops bit is ?1 ?, stereo line output enters power-save mode. pop noise at power-up/down can be reduced by changing pmlo bit at lo ps bit = ?1?. in this case, output signal line should be pulled-down to avss by 20k after ac coupled as figure 32 . rise/fall time is 300ms (max) at c=1 f. when pmlo bit = ?1? and lops bit = ?0?, stereo line output is in normal operation. lovl bit set the gain of stereo line output. dac ?dacl? lout pin rout pin ?lovl? figure 31. stereo line output lops pmlo mode lout/rout pin 0 power-down pull-down to avss (default) 0 1 normal operation normal operation 0 power-save fall down to avss 1 1 power-save rise up to vcom table 40. stereo line output mode select (x: don?t care) lovl1-0 bits gain 00 0db (default) 01 +2db 10 +4db 11 +6db table 41. stereo line output volume setting lout rout 1 f 220 20k figure 32. external circuit for stereo line ou tput (in case of using pop reduction circuit)
[ak4646] ms0557-e-05 2011/01 - 48 - [stereo line output control sequence (i n case of using pop reduction circuit)] pmlo bit lo p s bit lout, rout pins (1) (2) norm al output (3) (4) (5) (6) 300 m s 300 m s figure 33. stereo line output control seque nce (in case of using pop reduction circuit) (1) set lops bit = ?1?. stereo line out put enters the power-save mode. (2) set pmlo bit = ?1?. stereo line output exits the power-down mode. lout and rout pins rise up to vcom volta ge. rise time is 200ms (max 300ms) at c=1 f. (3) set lops bit = ?0? after lout and rout pins rise up. stereo line output exits the power-save mode. stereo line output is enabled. (4) set lops bit = ?1?. stereo line output enters power-save mode. (5) set pmlo bit = ?0?. stereo line output enters power-down mode. lout and rout pins fall down to avss. fall time is 200ms (max 300ms) at c=1 f. (6) set lops bit = ?0? after lout and rout pins fall down. stereo line output exits the power-save mode.
[ak4646] ms0557-e-05 2011/01 - 49 - speaker output power supply for speaker-amp (svdd) is 2.2v to 4.0v. in case of dynamic (electromagnetic) speaker (load resistance < 50 ), svdd is 2.2v to 3.6v. speaker type dynamic speaker piezo (ceramic) speaker load resistance (min) 8 50 ( note 20 ) load capacitance (max) 30pf 3 f ( note 20 ) note 20. load impedance is total impedance of series re sistance and piezo speaker impe dance at 1khz in 38hfigure 34. load capacitance is capacitan ce of piezo speaker. when piezo speaker is used, 10 or more series resistors should be connected at both spp and spn pins, respectively. table 42. speaker type and power supply range the dac output signal is input to the speaker-amp as [(l+r )/2]. the speaker-amp is mono and btl output. the gain is set by spkg1-0 bits. output level de pends on avdd voltage and spkg1-0 bits. gain spkg1-0 bits alc2 bit = ?0? alc2 bit = ?1? 00 +4.6db +6.6db (default) 01 +6.6db +8.6db 10 +8.6db +10.6db 11 +10.6db +12.6db table 43. spk-amp gain spk-amp output (dac input = 0dbfs) spkg1-0 bits alc2 bit = ?0? alc2 bit = ?1? (lmth1-0 bits = ?00?) 00 3.37vpp 3.17vpp 01 4.23vpp ( note 40 ) 4.00vpp 10 5.33vpp ( note 40 ) 5.04vpp ( note 40 ) 11 6.71vpp ( note 40 ) 6.33vpp ( note 40 ) note 40. the output level is calculated by assuming that output signal is not clippe d. in actual case, output signal may be clipped when dac outputs 0db fs signal. dac output level should be set to lower level by setting digital volume so that speaker-amp output level is 4. 0vpp or less and output si gnal is not clipped. table 44. spk-amp output level
[ak4646] ms0557-e-05 2011/01 - 50 - when a piezo speaker is used, resistances more than 10 should be inserted between spp/spn pins and speaker in series, respectively, as shown in figure 34 . zener diodes should be inserted between speaker and gnd as shown in figure 34 , in order to protect spk-amp of ak4646 from the power that the pi ezo speaker outputs when the sp eaker is pressured. zener diodes of the following zener voltage should be used. 0.92 x svdd zener voltage of zener diodo (zd in figure 34 ) svdd+0.3v ex) in case of svdd = 3.8v: 3.5v zd 4.1v for example, zener diode which zener voltage is 3.9v (min: 3.7v, max: 4.1v) can be used. spp spk-amp spn figure 34. speaker output circuit (in case of using piezo spearker)
[ak4646] ms0557-e-05 2011/01 - 51 - speaker-amp is powered-up/down by pmspk bit. when pmspk bit is ?0?, both spp and spn pins are in hi-z state. when pmspk bit is ?1? and sppsn bit is ?0?, the speaker-amp enters power-save mode. in this mode, spp pin is placed in hi-z state and spn pi n goes to svdd/2 voltage. when the pmspk bit is ? 1 ? after pdn pin is controlled from ? l ? to ? h ? , the spp and spn pins rise up from power-save-mode. in this mode, the spp pin is placed in a hi-z state and the spn pin goe s to svdd/2 voltage. because the spp and spn pins rise up at power-save-mode, this m ode can reduce pop noise. when the ak4646 is powered-down, pop noise can be also reduced by first entering power-save-mode. pmspk sppsn mode spp spn 0 x power-down hi-z hi-z (default) 0 power-save hi-z svdd/2 1 1 normal operation normal operation normal operation table 45. speaker-amp mode setting (x: don?t care) pmspk bit sppsn bit spp pin spn pin svdd/2 svdd/2 hi-z hi-z hi-z hi-z >1ms figure 35. power-up/power-down timing for speaker-amp
[ak4646] ms0557-e-05 2011/01 - 52 - serial control interface internal registers may be written by using the 3-wire p interface pins (c sn, cclk and cdtio). the data on this interface consists of read/write, register address (msb first, 7bits ) and control data (msb first, 8bits). each bit is clocked in on the rising edge (? ?) of cclk. it is available for writing data on the rising edge of csn. when reading operation, cdtio pin has become an out put mode at the falling edge of 8 th cclic and outputs d7-d0. the output finishes on the rising edge of csn. the cdtio is placed in a hi-z state except outputting data at read operation mode. clock speed of cclk is 5mhz (max). the value of internal registers are initialized by pdn pin = ?l?. note 41. it is available for reading the a ddress 00h~11h. when reading the address 12h 7fh, the register values are invalid. csn cclk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cdtio a6 a5 a2 a3 a1 a0 a4 d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w: read/write (?1?: write, ?0?: read) a6-a0: register address d7-d0: control data (input) at write command output data (output) at read command ?h? or ?l? ?h? or ?l? ?h? or ?l? ?h? or ?l? figure 36. serial control i/f timing
[ak4646] ms0557-e-05 2011/01 - 53 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 0 pmvcm pmbp pmspk pmlo pmdac 0 pmadl 01h power management 2 0 0 0 0 m/s 0 mcko pmpll 02h signal select 1 sppsn beeps dacs dacl 0 pmmp mgain2 mgain0 03h signal select 2 dafil lops mgain1 spkg1 spkg0 beepl lovl1 lovl0 04h mode control 1 pll3 pll2 pll1 pll0 bcko 0 dif1 dif0 05h mode control 2 ps1 ps0 fs3 0 0 fs2 fs1 fs0 06h timer select 0 wtm2 ztm 1 ztm0 wtm1 wtm0 rfst1 rfst0 07h alc mode control 1 lfst alc2 alc1 zelmn lmat1 lmat0 rgain0 lmth0 08h alc mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 09h lch input volume control ivl7 ivl6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 0ah output volume control ovl 7 ovl6 ovl5 ovl4 ovl 3 ovl2 ovl1 ovl0 0bh alc mode control 3 rgain1 lmth1 oref5 oref4 oref3 oref2 oref1 oref0 0ch rch input volume control ivr7 ivr6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 0dh alc level vol7 vol6 vol 5 vol4 vol3 vol2 vol1 vol0 0eh mode control 3 read loop smute ovolc datt1 datt0 dem1 dem0 0fh mode control 4 0 0 0 fr ivolc 0 0 0 10h power management 3 0 0 0 mdif2 mdif1 inr inl pmadr 11h digital filter select 1 gn1 gn0 lpf hpf eq0 fil3 0 hpfad 12h fil3 co-efficient 0 f3a7 f3a6 f3a5 f3a4 f3a3 f3a2 f3a1 f3a0 13h fil3 co-efficient 1 f3as 0 f3a13 f3a12 f3a11 f3a10 f3a9 f3a8 14h fil3 co-efficient 2 f3b7 f3b6 f3b5 f3b4 f3b3 f3b2 f3b1 f3b0 15h fil3 co-efficient 3 0 0 f3b13 f3b12 f3b11 f3b10 f3b9 f3b8 16h eq0-efficient 0 e0a7 e0a6 e0a5 e0a4 e0a3 e0a2 e0a1 e0a0 17h eq0-efficient 1 e0a15 e0a14 e0 a13 e0a12 e0a11 e0a10 e0a9 e0a8 18h eq0-efficient 2 e0b7 e0b6 e0b5 e0b4 e0b3 e0b2 e0b1 e0b0 19h eq0-efficient 3 0 0 e0b13 e0b12 e0b11 e0b10 e0b9 e0b8 1ah eq0-efficient 4 e0c7 e0c6 e0c5 e0c4 e0c3 e0c2 e0c1 e0c0 1bh eq0-efficient 5 e0c15 e0c14 e0c13 e0c12 e0c11 e0c10 e0c9 e0c8 1ch hpf co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 1dh hpf co-efficient 1 0 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 1eh hpf co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 1fh hpf co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 20h reserved 0 0 0 0 0 0 0 0 21h reserved 0 0 0 0 0 0 0 0 22h reserved 0 0 0 0 0 0 0 0 23h reserved 0 0 0 0 0 0 0 0 24h reserved 0 0 0 0 0 0 0 0 25h rch output volume control ovr7 ovr6 ovr5 ovr4 ovr3 ovr2 ovr1 ovr0 26h reserved 0 0 0 0 0 0 0 0 27h reserved 0 0 0 0 0 0 0 0 28h reserved 0 0 0 0 0 0 0 0 29h reserved 0 0 0 0 0 0 0 0 2ah reserved 0 0 0 0 0 0 0 0 2bh reserved 0 0 0 0 0 0 0 0 2ch lpf co-efficient 0 f2a7 f2a6 f2a5 f2a4 f2a3 f2a2 f2a1 f2a0 2dh lpf co-efficient 1 0 0 f2a13 f2a12 f2a11 f2a10 f2a9 f2a8 2eh lpf co-efficient 2 f2b7 f2b6 f2b5 f2b4 f2b3 f2b2 f2b1 f2b0 2fh lpf co-efficient 3 0 0 f2b13 f2b12 f2b11 f2b10 f2b9 f2b8
[ak4646] ms0557-e-05 2011/01 - 54 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 30h digital filter select 2 0 0 0 eq5 eq4 eq3 eq2 eq1 31h reserved 0 0 0 0 0 0 0 0 32h e1 co-efficient 0 e1a7 e1a6 e1a5 e1a4 e1a3 e1a2 e1a1 e1a0 33h e1 co-efficient 1 e1a15 e1a14 e1 a13 e1a12 e1a11 e1a10 e1a9 e1a8 34h e1 co-efficient 2 e1b7 e1b6 e1b5 e1b4 e1b3 e1b2 e1b1 e1b0 35h e1 co-efficient 3 e1b15 e1b14 e1b13 e1b12 e1b11 e1b10 e1b9 e1b8 36h e1 co-efficient 4 e1c7 e1c6 e1c5 e1c4 e1c3 e1c2 e1c1 e1c0 37h e1 co-efficient 5 e1c15 e1c14 e1c13 e1c12 e1c11 e1c10 e1c9 e1c8 38h e2 co-efficient 0 e2a7 e2a6 e2a5 e2a4 e2a3 e2a2 e2a1 e2a0 39h e2 co-efficient 1 e2a15 e2a14 e2 a13 e2a12 e2a11 e2a10 e2a9 e2a8 3ah e2 co-efficient 2 e2b7 e2b6 e2b5 e2b4 e2b3 e2b2 e2b1 e2b0 3bh e2 co-efficient 3 e2b15 e2b14 e2b13 e2b12 e2b11 e2b10 e2b9 e2b8 3ch e2 co-efficient 4 e2c7 e2c6 e2c5 e2c4 e2c3 e2c2 e2c1 e2c0 3dh e2 co-efficient 5 e2c15 e2c14 e2c13 e2c12 e2c11 e2c10 e2c9 e2c8 3eh e3 co-efficient 0 e3a7 e3a6 e3a5 e3a4 e3a3 e3a2 e3a1 e3a0 3fh e3 co-efficient 1 e3a15 e3a14 e3 a13 e3a12 e3a11 e3a10 e3a9 e3a8 40h e3 co-efficient 2 e3b7 e3b6 e3b5 e3b4 e3b3 e3b2 e3b1 e3b0 41h e3 co-efficient 3 e3b15 e3b14 e3b13 e3b12 e3b11 e3b10 e3b9 e3b8 42h e3 co-efficient 4 e3c7 e3c6 e3c5 e3c4 e3c3 e3c2 e3c1 e3c0 43h e3 co-efficient 5 e3c15 e3c14 e3c13 e3c12 e3c11 e3c10 e3c9 e3c8 44h e4 co-efficient 0 e4a7 e4a6 e4a5 e4a4 e4a3 e4a2 e4a1 e4a0 45h e4 co-efficient 1 e4a15 e4a14 e4 a13 e4a12 e4a11 e4a10 e4a9 e4a8 46h e4 co-efficient 2 e4b7 e4b6 e4b5 e4b4 e4b3 e4b2 e4b1 e4b0 47h e4 co-efficient 3 e4b15 e4b14 e4b13 e4b12 e4b11 e4b10 e4b9 e4b8 48h e4 co-efficient 4 e4c7 e4c6 e4c5 e4c4 e4c3 e4c2 e4c1 e4c0 49h e4 co-efficient 5 e4c15 e4c14 e4c13 e4c12 e4c11 e4c10 e4c9 e4c8 4ah e5 co-efficient 0 e5a7 e5a6 e5a5 e5a4 e5a3 e5a2 e5a1 e5a0 4bh e5 co-efficient 1 e5a15 e5a14 e5a13 e5a12 e5a11 e5a10 e5a9 e5a8 4ch e5 co-efficient 2 e5b7 e5b6 e5b5 e5b4 e5b3 e5b2 e5b1 e5b0 4dh e5 co-efficient 3 e5b15 e5b14 e5b13 e5b12 e5b11 e5b10 e5b9 e5b8 4eh e5 co-efficient 4 e5c7 e5c6 e5c5 e5c4 e5c3 e5c2 e5c1 e5c0 4fh e5 co-efficient 5 e5c15 e5c14 e5c13 e5c12 e5c11 e5c10 e5c9 e5c8 note 42. pdn pin = ?l? resets the registers to their default values. note 43. unused bits must contain a ?0? value. note 44. reading of address 26h ~ 2fh, 12h ~ 24h and 32h ~ 7fh are not possible. note 45. address 0dh is a read only register. writing access to 0dh does not effect the operation.
[ak4646] ms0557-e-05 2011/01 - 55 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 0 pmvcm pmbp pmspk pmlo pmdac 0 pmadl r/w r r/w r/w r/ w r/w r/w r r/w default 0 0 0 0 0 0 0 0 pmadl: mic-amp lch and adc lch power management 0: power-down (default) 1: power-up when the pmadl or pmadr bit is changed from ?0 ? to ?1?, the initialization cycle (1059/fs=24ms @44.1khz) starts. after initializing, digital data of the adc is output. pmdac: dac power management 0: power-down (default) 1: power-up pmlo: stereo line out power management 0: power-down (default) 1: power-up pmspk: speaker-amp power management 0: power-down (default) 1: power-up pmbp: min input power management 0: power-down (default) 1: power-up both pmdac and pmbp bits should be set to ?1? when dac is powered-up for playback. after that, beepl or beeps bit is used to control each path when min input is used. pmvcm: vcom power management 0: power-down (default) 1: power-up when any blocks are powered-up, th e pmvcm bit must be set to ?1?. pmvcm bit can be set to ?0? only when all power management bits of 00h, 01h,02h, 10h and mcko bits are ?0?. each block can be powered-down respectivel y by writing ?0? in each bit of this a ddress. when the pdn pin is ?l?, all blocks are powered-down regardless as setting of this address. in this case, regist er is initialized to the default value. when all power management bits are ?0? in the 00h, 01h, 02h and 10h addresses and mcko bit is ?0?, all blocks are powered-down. the register values remain unchanged. when neither adc nor dac are used, external clocks may not be present. when adc or dac is used, external clocks must always be present.
[ak4646] ms0557-e-05 2011/01 - 56 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h power management 2 0 0 0 0 m/s 0 mcko pmpll r/w r r r r r/w r r/w r/w default 0 0 0 0 0 0 0 0 pmpll: pll power management 0: ext mode and power-down (default) 1: pll mode and power-up mcko: master clock output enable 0: disable: mcko pin = ?l? (default) 1: enable: output frequency is selected by ps1-0 bits. m/s: master / slave mode select 0: slave mode (default) 1: master mode addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h signal select 1 sppsn beeps dacs dacl 0 pmmp mgain2 mgain0 r/w r/w r/w r/w r/ w r r/w r/w r/w default 0 0 0 0 0 0 0 1 mgain2-0: mic-amp gain control ( table 19 ) mgain1 bit is d5 bit of 03h. pmmp: mpwr pin power management 0: power-down: hi-z (default) 1: power-up dacl: switch control from dac to stereo line output 0: off (default) 1: on when pmlo bit is ?1?, dacl bit is enabled. when pmlo bit is ?0?, the lout/rout pins go to avss. dacs: switch control from dac to speaker-amp 0: off (default) 1: on when dacs bit is ?1?, dac output signal is input to speaker-amp. beeps: switch control from min pin to speaker-amp 0: off (default) 1: on when beeps bit is ?1?, mono signal is input to speaker-amp. sppsn: speaker-amp power-save mode 0: power-save mode (default) 1: normal operation when sppsn bit is ?0?, speaker-amp is on power-save mode. in this mode, spp pin goes to hi-z and spn pin is outputs svdd/2 voltage. when pmspk bit = ?1?, sppsn bit is enabled. after the pdn pin is set to ?l?, speaker-amp is in power-down mode since pmspk bit is ?0?.
[ak4646] ms0557-e-05 2011/01 - 57 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h signal select 2 dafil lops mgain1 spkg1 spkg0 beepl lovl1 lovl0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 lovl1-0: output stereo line gain select ( table 41 ) default: 00(0db) beepl: switch control from min pin to stereo line output 0: off (default) 1: on when pmlo bit is ?1?, beepl bit is enabled. when pmlo bit is ?0 ?, the lout/rout pins go to avss. spkg1-0: speaker-amp output gain select ( table 43 ) mgain1: mic-amp gain control ( table 19 ) lops: stereo line ou tput power-save mode 0: normal operation (default) 1: power-save mode dafil: filter/alc path select when pmadl bit = ?1? or pmadr bit = ?1? 0: adc/recording path (default) 1: dac/playback path the sdto pin outputs ?l? with regard less of pmadl and pmadr bits when dafil bit = ?1? and pmdac bit = ?1?. addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h mode control 1 pll3 pll2 pll1 pll0 bcko 0 dif1 dif0 r/w r/w r/w r/w r/ w r/w r r/w r/w default 0 0 0 0 0 0 1 0 dif1-0: audio interface format ( table 16 ) default: ?10? (left justified) bcko: bick output frequenc y select at master mode ( table 10 ) pll3-0: pll reference clock select ( table 4 ) default: ?0000? (lrck pin) addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h mode control 2 ps1 ps0 fs3 0 0 fs2 fs1 fs0 r/w r/w r/w r/w r r r/w r/w r/w default 0 0 0 0 0 0 0 0 fs3-0: sampling frequency select ( table 5 and table 6 ) and mcki frequency select ( table 11 ) fs3-0 bits select sampling frequency at p ll mode and mcki frequency at ext mode. ps1-0: mcko output frequency select ( table 9 ) default: ?00? (256fs)
[ak4646] ms0557-e-05 2011/01 - 58 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h timer select 0 wtm2 ztm 1 ztm0 wtm1 wtm0 rfst1 rfst0 r/w r r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 wtm2-0: alc recovery waiting period ( table 26 ) a period of recovery operation when any limiter operation does not occur dur ing the alc1 operation default is ?000? (128/fs). ztm1-0: alc limiter/recovery oper ation zero crossing timeout period ( table 25 ) when the ipga perform zero crossing or tim eout, the ipga value is changed by the p write operation, alc1 recovery operation. de fault is ?00? (128/fs). rfst1-0: alc fast recovery speed ( table 30 ) default: ?00? (4times) addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h alc mode control 1 lfst alc2 alc1 zelmn lmat1 lmat0 rgain0 lmth0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 lmth1-0: alc limiter detection level / recovery counter reset level ( table 23 ) default: ?00? lmth1 bit is d6 bit of 0bh. rgain1-0: alc recovery gain step ( table 27 ) default: ?00? rgain1 bit is d7 bit of 0bh. lmat1-0: alc limiter att step ( table 24 ) default: ?00? zelmn: zero crossing detection enab le at alc limiter operation 0: enable (default) 1: disable alc1: alc enable for recording 0: recording alc disable (default) 1: recording alc enable alc2: alc enable for playback 0: playback alc disable (default) 1: playback alc enable lfst: limiter function of alc when the output was bigger than fs. 0: output is zero crossing or being changed value of volume at the time of the output is zero crossing time out. 1: when output of alc is bigger than fs, vol value is changed instantly.
[ak4646] ms0557-e-05 2011/01 - 59 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h alc mode control 2 iref7 iref6 i ref5 iref4 iref3 iref2 iref1 iref0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 1 1 0 0 0 0 1 ref7-0: reference value at alc recove ry operation. 0.375db step, 242 level ( table 28 ) default: ?e1h? (+30.0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h lch input volume control ivl7 iv l6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 0ch rch input volume control ivr7 ivr6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 1 1 0 0 0 0 1 ivl7-0, ivr7-0: input digital volume; 0.375db step, 242 level ( table 34 ) default: ?e1h? (+30.0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah lch digital volume control ovl7 ovl6 ovl5 ovl4 ovl3 ovl2 ovl1 ovl0 25h rch digital volume control ovr7 ovr6 ovr5 ovr4 ovr3 ovr2 ovr1 ovr0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 0 0 1 0 0 0 1 ovl7-0, ovr7-0: output digital volume ( table 35 ) default: ?91h? (0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh alc mode control 3 rgain1 lmth1 oref5 oref4 oref3 oref2 oref1 oref0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 1 0 1 0 0 0 oref5-0: reference value at playback alc recovery operation. 0.375db step, 50 level ( table 29 ) default: ?28h? (+6.0db) lmth1: alc limiter detection level / recovery counter reset level ( table 23 ) rgain1: alc recovery gain step ( table 27 ) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh alc volume vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 r/w r r r r r r r r default - - - - - - - - vol7-0: current alc volume value; 0.375db step, 242 lev el. read operation only ( table 31 )
[ak4646] ms0557-e-05 2011/01 - 60 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh mode control 3 read loop smute ovolc datt1 datt0 dem1 dem0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 1 0 0 0 1 dem1-0: de-emphasis frequency select ( table 37 ) default: ?01? (off) datt1-0: output digital volume2; 6db step, 4 level ( table 36 ) default: ?00h? (0.0db) ovolc: output digital volu me control mode select 0: independent 1: dependent (default) when ovolc bit = ?1?, ovl7-0 bits control both lch and rch volume level, while register values of ovl7-0 bits are not written to ovr7-0 bits. when ovol c bit = ?0?, ovl7-0 bits control lch level and ovr7-0 bits control rch level, respectively. smute: soft mute control 0: normal operation (default) 1: dac outputs soft-muted loop: digital loopback mode 0: sdti dac (default) 1: sdto dac read: read function enable 0: disable (default) 1: enable addr register name d7 d6 d5 d4 d3 d2 d1 d0 0fh mode control 4 0 0 0 fr ivolc 0 0 0 r/w r r r r/w r/w r r r default 0 0 0 0 1 0 0 0 ivolc: input digital volume control mode select 0: independent 1: dependent (default) when ivolc bit = ?1?, ivl7-0 bits control both lch and rch volume level, while register values of ivl7-0 bits are not written to ivr7-0 bits. when ivolc bit = ?0?, ivl7-0 bits control lch level and ivr7-0 bits control rch level, respectively. fr: alc fast recovery function enable 0: enable (default) 1: disable
[ak4646] ms0557-e-05 2011/01 - 61 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h power management 3 0 0 0 mdif2 mdif1 inr inl pmadr r/w r r r r/w r/ w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmadr: mic-amp lch and adc rch power management 0: power-down (default) 1: power-up inl: adc lch input source select 0: lin1 pin (default) 1: lin2 pin inr: adc rch input source select 0: rin1 pin (default) 1: rin2 pin mdif1: adc lch input type select 0: single-ended input (l in1/lin2 pin: default) 1: full-differential input (in1+/in1 ? pin) mdif2: adc rch input type select 0: single-ended input (r in1/rin2 pin: default) 1: full-differential input (in2+/in2 ? pin) addr register name d7 d6 d5 d4 d3 d2 d1 d0 11h digital filter select 1 gn1 gn0 lpf hpf eq0 fil3 0 hpfad r/w r/w r/w r/w r/ w r/w r/w r r/w default 0 0 0 0 0 0 0 1 hpfad: hpf control of adc 0: disable 1: enable (default) when hpfad bit is ?1?, the settings of f1a13-0 and f1b13-0 bits are enabled. when hpfad bit is ?0?, hpfad block is through (0db). fil3: fil3 (stereo separation emphasi s filter) coefficient setting enable 0: disable (default) 1: enable when fil3 bit is ?1?, the settings of f3a13-0 and f3b13- 0 bits are enabled. when fi l3 bit is ?0?, fil3 block is off (mute). eq: eq (gain compensation filter) coefficient setting enable 0: disable (default) 1: enable when eq bit is ?1?, the settings of eqa15-0, eqb13-0 and eqc15-0 bits are enable d. when eq bit is ?0?, eq block is through (0db). hpf: hpf coefficient setting enable 0: disable (default) 1: enable when hpf bit is ?1?, the settings of f1a13-0 and f1b13- 0 bits are enabled. when hpf bit is ?0?, hpf block is through (0db).
[ak4646] ms0557-e-05 2011/01 - 62 - lpf: lpf coefficient setting enable 0: disable (default) 1: enable when lpf bit is ?1?, the settings of f2a13-0 and f2b13- 0 bits are enabled. when lpf bit is ?0?, lpf block is through (0db). gn1-0: gain select at gain block ( table 22 ) default: ?00? addr register name d7 d6 d5 d4 d3 d2 d1 d0 12h fil3 co-efficient 0 f3a7 f3a6 f3a5 f3a4 f3a3 f3a2 f3a1 f3a0 13h fil3 co-efficient 1 f3as 0 f3a13 f3a12 f3a11 f3a10 f3a9 f3a8 14h fil3 co-efficient 2 f3b7 f3b6 f3b5 f3b4 f3b3 f3b2 f3b1 f3b0 15h fil3 co-efficient 3 0 0 f3b13 f3b12 f3b11 f3b10 f3b9 f3b8 16h eq0-efficient 0 e0a7 e0a6 e0a5 e0a4 e0a3 e0a2 e0a1 e0a0 17h eq0-efficient 1 e0a15 e0a14 e0a13 e0a12 e0a11 e0a10 e0a9 e0a8 18h eq0-efficient 2 e0b7 e0b6 e0b5 e0b4 e0b3 e0b2 e0b1 e0b0 19h eq0-efficient 3 0 0 e0b13 e0b12 e0b11 e0b10 e0b9 e0b8 1ah eq0-efficient 4 e0c7 e0c6 e0c5 e0c4 e0c3 e0c2 e0c1 e0c0 1bh eq0-efficient 5 e0c15 e0c14 e0c13 e0c12 e0c11 e0c10 e0c9 e0c8 r/w w w w w w w w w default 0 0 0 0 0 0 0 0 f3a13-0, f3b13-0: fil3 (stereo separati on emphasis filter) coefficient (14bit x 2) default: ?0000h? f3as: fil3 (stereo separation emphasis filter) select 0: hpf (default) 1: lpf eqa15-0, eqb13-0, eqc15-c0: eq (gain compen sation filter) coefficient (16bit x 2 + 14bit x 1) default: ?0000h? addr register name d7 d6 d5 d4 d3 d2 d1 d0 1ch hpf co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 1dh hpf co-efficient 1 0 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 1eh hpf co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 1fh hpf co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 r/w w w w w w w w w default f1a13-0 bits = 0x1fa9, f1b13-0 bits = 0x20ad f1a13-0, f1b13-0: fil1 (wind-noise reduction filter) coefficient (14bit x 2) default: f1a13-0 bits = 0x1fa9, f1b13-0 bits = 0x20ad fc = 150hz@fs=44.1khz addr register name d7 d6 d5 d4 d3 d2 d1 d0 2ch lpf co-efficient 0 f2a7 f2a6 f2a5 f2a4 f2a3 f2a2 f2a1 f2a0 2dh lpf co-efficient 1 0 0 f2a13 f2a12 f2a11 f2a10 f2a9 f2a8 2eh lpf co-efficient 2 f2b7 f2b6 f2b5 f2b4 f2b3 f2b2 f2b1 f2b0 2fh lpf co-efficient 3 0 0 f2b13 f2b12 f2b11 f2b10 f2b9 f2b8 r/w w w w w w w w w default 0 0 0 0 0 0 0 0 f2a13-0, f2b13-0: fil2 (lpf) coefficient (14bit x 2) default: ?0000h?
[ak4646] ms0557-e-05 2011/01 - 63 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 30h digital filter select 2 0 0 0 eq5 eq4 eq3 eq2 eq1 r/w r r r r/w r/ w r/w r/w r/w default 0 0 0 0 0 0 0 0 eq1: equalizer 1 coefficient setting enable 0: disable (default) 1: enable when eq1 bit is ?1?, the settings of e1a15-0, e1b15-0 and e1c15-0 bits are enable d. when eq1 bit is ?0?, eq1 block is through (0db). eq2: equalizer 2 coefficient setting enable 0: disable (default) 1: enable when eq2 bit is ?1?, the settings of e2a15-0, e2b15-0 and e2c15-0 bits are enable d. when eq2 bit is ?0?, eq2 block is through (0db). eq3: equalizer 3 coefficient setting enable 0: disable (default) 1: enable when eq3 bit is ?1?, the settings of e3a15-0, e3b15-0 and e3c15-0 bits are enable d. when eq3 bit is ?0?, eq3 block is through (0db). eq4: equalizer 4 coefficient setting enable 0: disable (default) 1: enable when eq4 bit is ?1?, the settings of e4a15-0, e4b15-0 and e4c15-0 bits are enable d. when eq4 bit is ?0?, eq4 block is through (0db). eq5: equalizer 5 coefficient setting enable 0: disable (default) 1: enable when eq5 bit is ?1?, the settings of e5a15-0, e5b15-0 and e5c15-0 bits are enable d. when eq5 bit is ?0?, eq5 block is through (0db).
[ak4646] ms0557-e-05 2011/01 - 64 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 32h e1 co-efficient 0 e1a7 e1a6 e1a5 e1a4 e1a3 e1a2 e1a1 e1a0 33h e1 co-efficient 1 e1a15 e1a14 e1a13 e1a12 e1a11 e1a10 e1a9 e1a8 34h e1 co-efficient 2 e1b7 e1b6 e1b5 e1b4 e1b3 e1b2 e1b1 e1b0 35h e1 co-efficient 3 e1b15 e1b14 e1b13 e1b12 e1b11 e1b10 e1b9 e1b8 36h e1 co-efficient 4 e1c7 e1c6 e1c5 e1c4 e1c3 e1c2 e1c1 e1c0 37h e1 co-efficient 5 e1c15 e1c14 e1c13 e1c12 e1c11 e1c10 e1c9 e1c8 38h e2 co-efficient 0 e2a7 e2a6 e2a5 e2a4 e2a3 e2a2 e2a1 e2a0 39h e2 co-efficient 1 e2a15 e2a14 e2a13 e2a12 e2a11 e2a10 e2a9 e2a8 3ah e2 co-efficient 2 e2b7 e2b6 e2b5 e2b4 e2b3 e2b2 e2b1 e2b0 3bh e2 co-efficient 3 e2b15 e2b14 e2b13 e2b12 e2b11 e2b10 e2b9 e2b8 3ch e2 co-efficient 4 e2c7 e2c6 e2c5 e2c4 e2c3 e2c2 e2c1 e2c0 3dh e2 co-efficient 5 e2c15 e2c14 e2c13 e2c12 e2c11 e2c10 e2c9 e2c8 3eh e3 co-efficient 0 e3a7 e3a6 e3a5 e3a4 e3a3 e3a2 e3a1 e3a0 3fh e3 co-efficient 1 e3a15 e3a14 e3a13 e3a12 e3a11 e3a10 e3a9 e3a8 40h e3 co-efficient 2 e3b7 e3b6 e3b5 e3b4 e3b3 e3b2 e3b1 e3b0 41h e3 co-efficient 3 e3b15 e3b14 e3b13 e3b12 e3b11 e3b10 e3b9 e3b8 42h e3 co-efficient 4 e3c7 e3c6 e3c5 e3c4 e3c3 e3c2 e3c1 e3c0 43h e3 co-efficient 5 e3c15 e3c14 e3c13 e3c12 e3c11 e3c10 e3c9 e3c8 44h e4 co-efficient 0 e4a7 e4a6 e4a5 e4a4 e4a3 e4a2 e4a1 e4a0 45h e4 co-efficient 1 e4a15 e4a14 e4a13 e4a12 e4a11 e4a10 e4a9 e4a8 46h e4 co-efficient 2 e4b7 e4b6 e4b5 e4b4 e4b3 e4b2 e4b1 e4b0 47h e4 co-efficient 3 e4b15 e4b14 e4b13 e4b12 e4b11 e4b10 e4b9 e4b8 48h e4 co-efficient 4 e4c7 e4c6 e4c5 e4c4 e4c3 e4c2 e4c1 e4c0 49h e4 co-efficient 5 e4c15 e4c14 e4c13 e4c12 e4c11 e4c10 e4c9 e4c8 4ah e5 co-efficient 0 e5a7 e5a6 e5a5 e5a4 e5a3 e5a2 e5a1 e5a0 4bh e5 co-efficient 1 e5a15 e5a14 e5a13 e5a12 e5a11 e5a10 e5a9 e5a8 4ch e5 co-efficient 2 e5b7 e5b6 e5b5 e5b4 e5b3 e5b2 e5b1 e5b0 4dh e5 co-efficient 3 e5b15 e5b14 e5b13 e5b12 e5b11 e5b10 e5b9 e5b8 4eh e5 co-efficient 4 e5c7 e5c6 e5c5 e5c4 e5c3 e5c2 e5c1 e5c0 4fh e5 co-efficient 5 e5c15 e5c14 e5c13 e5c12 e5c11 e5c10 e5c9 e5c8 r/w w w w w w w w w default 0 0 0 0 0 0 0 0 e1a15-0, e1b15-0, e1c15-0: equalizer 1 coefficient (16bit x3) default: ? 0000h ? e2a15-0, e2b15-0, e2c15-0: equalizer 2 coefficient (16bit x3) default: ? 0000h ? e3a15-0, e3b15-0, e3c15-0: equalizer 3 coefficient (16bit x3) default: ? 0000h ? e4a15-0, e4b15-0, e4c15-0: equalizer 4 coefficient (16bit x3) default: ? 0000h ? e5a15-0, e5b15-0, e5c15-0: equalizer 5 coefficient (16bit x3) default: ? 0000h ?
[ak4646] ms0557-e-05 2011/01 - 65 - system design figure 37 shows the system connection diagram for the ak4646. an evaluation board [akd4646] is available which demonstrates the optimum layout, power s upply arrangements and measurement results. nc rout lout min rin2 lin2 lin1 rin1 nc nc svss svdd s pp spn mcko mcki mpwr vcom a vss a vdd vcoc nc pdn csn dvss dvdd bi ck lrck sd to sd ti cdtio cclk a k4646 top view 2 5 26 27 28 29 30 31 32 24 23 22 1 1 6 15 14 13 12 11 10 9 21 20 19 18 17 2 3 4 5 6 7 8 2.2k 2.2k 2.2k 2.2 k external mic internal mic 0.1u 2.2u 0.1u rp power supply 2.2 3.6v 0.1u 0.1u 10 dsp p line out sp eaker mono in cp 10u analog ground d igital ground 1u 1u 200 200 20k 20k zd2 zd 1 dynamic spk r1, r2: s hort zd1, zd2: open piezo spk r1, r2: 10 zd1, zd2: required r1 r2 notes: - avss, dvss and svss of the ak4646 should be dist ributed separately from the ground of external controllers. - all digital input pins s hould not be left floating. - when the ak4646 is ext mode (pmpll bit = ?0?), a re sistor and capacitor of vcoc pin is not needed. - when the ak4646 is pll mode (pmpll bit = ?1?), a resistor and capacitor of vcoc pin is shown in table 4 . - when piezo speaker is used, 2.2 4.0v power should be supplied to svdd and 10 or more series resistors should be connected to both spp and spn pins, respectively. - when the ak4646 is used at master mode, lrck and bick pins are floating before m/s bit is changed to ?1?. therefore, around 100k pull-up resistor should be connected to lrck and bick pins of the ak4646. figure 37. system connection diagram
[ak4646] ms0557-e-05 2011/01 - 66 - 1. grounding and power supply decoupling the ak4646 requires careful attention to power s upply and grounding arrangement s. avdd, dvdd and svdd are usually supplied from the system?s analog supply. if avdd, dvdd and svdd are supplied separately, the power-up sequence is not critical. avss, dvss and svss of the ak4646 should be connected to the analog ground plane. system analog ground and digital ground should be c onnected together near to where th e supplies are brought onto the printed circuit board. decoupling capacitors should be as near to th e ak4646 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference vcom is a signal ground of this chip. a 2.2 f electrolytic capacitor in parallel with a 0.1 f ceramic capacitor should be attached to the vcom pin eliminates the effects of high frequency noise. no lo ad current may be drawn from the vcom pin. all signals, especially clocks, shoul d be kept away from the vcom pin in or der to avoid unwanted coupling into the ak4646. 3. analog inputs the mic, line and min inputs are singl e-ended. the inputs signal range scal es with nominally at 0.0636 x avdd vpp (typ) for the mic input and 0.636 x avdd vpp (typ) for the mi n input, centered around the internal common voltage (0.5 x avdd). usually the input signal is ac coupled usi ng a capacitor. the cut-off frequency is fc = 1/ (2 rc). the ak4646 can accept input voltages from avss to avdd. 4. analog outputs the input data format for the dac is 2?s complement. the output voltage is a positive full scale for 7fffh (@16bit) and a negative full scale for 8000h (@16bit). the ideal output is vcom voltage for 0000h (@16bit) . stereo line output is centered at 0.5 x avdd (typ). the headphone-amp a nd speaker-amp outputs are centered at svdd/2.
[ak4646] ms0557-e-05 2011/01 - 67 - control sequence clock set up when adc or dac is powered-up, the clocks must be supplied. 1. pll master mode. bick pin lrck pin mcko bit (addr:01h, d1) pmpll bit (addr:01h, d0) 40msec(max) output (1) (6) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) mcki pin (5) (4) input m/s bit (addr:01h, d3) mcko pin output (8) (7) 40msec(max) example: audio i/f format: msb justified (adc & dac) bick frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz mcko: enable sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3)addr:00h, data:40h (2)addr:01h, data:08h addr:04h, data:4ah addr:05h, data:27h (4)addr:01h, data:0bh mcko, bick and lrck output figure 38. clock set up sequence (1) (1) after power up, pdn pin = ?l? ? ?h? ?l? time of 150ns or more is needed to reset the ak4646. (2) dif1-0, pll3-0, fs3-0, bcko and m/s bits should be set during this period. (3) power up vcom: pmvcm bit = ?0? ? ?1? vcom should first be powered-up be fore the other block operates. (4) in case of using mcko output: mcko bit = ?1? in case of not using mcko output: mcko bit = ?0? (5) pll lock time is 40ms (max) after pmpll bit changes fro m ?0? to ?1? and mcki is supplied from an external source. (6) the ak4646 starts to output the lrck and bick clocks after the pll becomes stable. then normal operation starts. (7) the invalid frequency is output from mcko pi n during this period if mcko bit = ?1?. (8) the normal clock is output from mcko pin afte r the pll is locked if mcko bit = ?1?.
[ak4646] ms0557-e-05 2011/01 - 68 - 2. pll slave mode (lrck or bick pin) pmpll bit (addr:01h, d0) internal clock (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) lrck pin bick pin (4) (5) input 4fs of example: audio i/f format : msb justified (adc & dac) pll reference clock: bick bick frequency: 64fs sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3) addr:00h, data:40h (2) addr:04h, data:32h addr:05h, data:27h (4) addr:01h, data:01h figure 39. clock set up sequence (2) (1) after power up: pdn pin ?l? ? ?h? ?l? time of 150ns or more is needed to reset the ak4646. (2) dif1-0, fs3-0 and pll3-0 bits s hould be set during this period. (3) power up vcom: pmvcm bit = ?0? ? ?1? vcom should first be powered up be fore the other block operates. (4) pll starts after the pmpll bit cha nges from ?0? to ?1? and pll reference clock (lrck or bick pin) is supplied. pll lock time is 160ms (max) when lrck is a pll reference clock. and pll lock time is 2ms (max) when bick is a pll reference clock. (5) normal operation stats after that the pll is locked.
[ak4646] ms0557-e-05 2011/01 - 69 - 3. pll slave mode (mcki pin) bick pin lrck pin mcko bit (addr:01h, d1) pmpll bit (addr:01h, d0) (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) mcki pin (5) (4) input mcko pin output (6) (7) 40msec(max) (8) input example: audio i/f format: msb justified (adc & dac) bick frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz mcko: enable (1) power supply & pdn pin = ?l? ? ?h? (3)addr:00h, data:40h (2)addr:04h, data:4ah addr:05h, data:27h (4)addr:01h, data:03h mcko output start bick and lrck input start figure 40. clock set up sequence (3) (1) after power up: pdn pin ?l? ? ?h? ?l? time of 150ns or more is needed to reset the ak4646. (2) dif1-0, pll3-0, fs3-0, bcko and m/s b its should be set during this period. (3) power up vcom: pmvcm bit = ?0? ? ?1? vcom should first be powered up be fore the other block operates. (4) enable mcko output: mcko bit = ?1? (5) pll starts after that the pmpll b it changes from ?0? to ?1? and pll refe rence clock (mcki pin) is supplied. pll lock time is 40ms (max). (6) the normal clock is output from mcko after pll is locked. (7) the invalid frequency is output from mcko during this period. (8) bick and lrck clocks should be synchronized with mcko clock.
[ak4646] ms0557-e-05 2011/01 - 70 - 4. ext slave mode (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) lrck pin bick pin (4) input (4) mcki pin input example: audio i/f format: msb justified (adc and dac) input mcki frequency: 1024fs mcko: disable (1) power supply & pdn pin = ?l? ? ?h? (3) addr:00h, data:40h (2) addr:04h, data:02h addr:05h, data:27h mcki, bick and lrck input figure 41. clock set up sequence (4) (1) after power up: pdn pin ?l? ? ?h? ?l? time of 150ns or more is needed to reset the ak4646. (2) dif1-0 and fs1-0 bits shoul d be set during this period. (3) power up vcom: pmvcm bit = ?0? ? ?1? vcom should first be powered up be fore the other block operates. (4) normal operation starts after the mcki, lrck and bick are supplied.
[ak4646] ms0557-e-05 2011/01 - 71 - mic input recording (stereo) fs3-0 bits (addr:05h, d5&d2-0) mic control (addr:02h, d2-0) pmadl/r bit (addr:00h&10h, d0) adc internal state 1,111 0,000 001 101 power down initialize normal state power down 1059 / fs (1) (2) (7) alc state alc enable alc disable alc disable (5) alc control 1 (addr:06h) 00h 3ch (3) alc control 2 (addr:08h) e1h e1h (4) alc control 3 (addr:0bh) 28h 28h (8) (6) alc control 4 (addr:07h) 00h 21h 01h (9) example: pll master mode audio i/f format:msb justified (adc & dac) pre mic amp:+20db sampling frequency:44.1khz mic power on alc setting:refer to figrure 23 alc1 bit=?1? (2) addr:02h, data:05h (3) addr:06h, data:3ch (1) addr:05h, data:27h (4) addr:08h, data:e1h (5) addr:0bh, data:28h (7) addr:00h, data:41h addr:10h, data:01h recording (8) addr:00h, data:40h addr:10h, data:00h (6) addr:07h, data:21h (9) addr:07h, data:01h figure 42. mic input recording sequence this sequence is an example of alc setting at fs=44.1kh z. for changing the parameter of alc, please refer to ? figure 29. registers set-up sequence at alc operation? at first, clocks should be supplied according to ?clock set up? sequence. (1) set up a sampling frequency (fs3-0 bit). when the ak 4646 is pll mode, mic and adc should be powered-up in consideration of pll lock time after a sampling frequency is changed. (2) set up mic input (addr: 02h) (3) set up timer select for alc (addr: 06h) (4) set up iref value for alc (addr: 08h) (5) set up lmth1 and rgain1 bits (addr: 0bh) (6) set up lmth0, rgain0, lmat1-0 and alc bits (addr: 07h) (7) power up mic and adc: pmadl = pmadr bits = ?0? ?1? the initialization cycle time of adc is 1059/fs=24ms@fs=44.1khz. after the alc bit is set to ?1? and mic&adc block is powered-up, the alc operation starts from ivol default value (+30db). the time of offset voltage going to ?0? after the adc initialization cycle depends on both the time of analog input pin going to the common voltage a nd the constant time of the offset can cel digital hpf. this time can be shorter by using the following sequence: at first, pmvcm and pmmp bits should set to ?1?. then, the adc should be powered-up. the waiting time to power-up the adc should be longer than 4 times of the tim e constant that is determined by the ac coupling capacitor at analog input pin and the internal input resistance 30k(typ). (8) power down mic and adc: pmadl = pmadr bits = ?1? ?0? when the registers for the alc operation are not change d, alc bit may be keeping ?1?. the alc operation is disabled because the mic&adc block is powered-down. if the registers for the alc operation are also changed when the sampling frequency is changed, it should be done after the ak4646 goes to the manual mode (alc bit = ?0?) or mic&adc block is powered-down (pmadl=pm adr bits = ?0?). ivol gain is not reset when pmadl=pmadr bits = ?0?, and then ivol operation starts from the setting valu e when pmadc or pmadr bit is changed to ?1?. (9) alc disable: alc bit = ?1? ?0?
[ak4646] ms0557-e-05 2011/01 - 72 - speaker-amp output fs3-0 bits (addr:05h, d5&d2-0) ovl/r7-0 bits (addr:0ah&0dh, d7-0) pmdac bit (addr:00h, d2) pmspk bit (addr:00h, d4) 1,111 0,000 91h 91h spp pin normal output sppsn bit (addr:02h, d7) hi-z hi-z spn pin normal output hi-z hi-z svdd/2 svdd/2 (1) (7) x 0 (6) alc2 bit (addr:07h, d6) (8) (9) (12) (10) dacs bit (addr:02h, d3) (11) 01 00 (3) spkg1-0 bits (addr:03h, d4-3) (2) (5) alc control 1 (addr:06h) 00h 3ch (4) alc control 2 (addr:0bh) 28h 28h pmbp bit (addr:00h, d5) example: pll master mode audio i/f format: msb justified (adc & dac) sampling frequency:44.1khz digital volume: 0db alc: enable (2) addr:02h, data:20h (6) addr:07h, data:40h (1) addr:05h, data:27h (7) addr:0ah & 0dh, data:91h (8) addr:00h, data:74h (9) addr:02h, data:a0h (10) addr:02h, data:20h playback (11) addr:02h, data:00h (12) addr:00h, data:40h (3) addr:03h, data:08h (4) addr:06h, data:3ch (5) addr:0bh, data:28h figure 43. speaker-amp output sequence at first, clocks should be supplied according to ?clock set up? sequence. (1) set up a sampling frequency (fs3-0 bits). when the ak4646 is pll mode, dac and speaker-amp should be powered-up in consideration of pll lock time after a sampling frequency is changed. (2) set up the path of ?dac ? spk-amp?: dacs bit = ?0? ? ?1? (3) spk-amp gain setting: spkg1-0 bits = ?00? ? ?01? (4) set up timer select for alc (addr: 06h) (5) set up ref value for alc (addr: 0bh) (6) set up lmth0, rgain0, lmat1-0 and alc2 bits (addr: 07h) (7) set up the output digital volume (addr: 0ah and 0dh). when ovolc bit is ?1? (default), ovl7- 0 bits set the volume of both channels. after dac is powered-up, the digital volume changes from default value (0db) to the re gister setting value by the soft transition. alc/ovol are invalid to dac when (pmadl bit = ?1? or pmadr bit = ?1?) and dafil bit = ?0?. (8) power up of dac, min-amp and speaker-amp: pmdac = pmbp = pmspk bits = ?0? o ?1? the dac outputs invalid voltage for 67/fs = 1.52ms@fs = 44.1khz after powered-up, then it starts outputting normal voltage. (9) exit the power-save-mode of speaker-amp: sppsn bit = ?0? o ?1? ? (9) ? time depends on the time constant of external resistor and capacitor connected to min pin. if speaker-amp output is enabled be fore input of min-amp becomes stable, pop noise may occur. e.g. r=20k, c=0.1 p f: recommended wait time is more than 5 w = 10ms. (10) enter the power-save-mode of speaker-amp: sppsn bit = ?1? o ?0? (11) disable the path of ?dac ? spk-amp?: dacs bit = ?1? ? ?0? (12) power down dac, min-amp and speaker-amp: pmdac = pmbp = pmspk bits = ?1? o ?0?
[ak4646] ms0557-e-05 2011/01 - 73 - mono signal output from speaker-amp dacs bit (addr:02h, d5) pmspk bit (addr:00h, d4) beeps bit (addr:02h, d6) spp pin normal output sppsn bit (addr:02h, d7) hi-z hi-z spn pin normal output hi-z hi-z svdd/2 svdd/2 (2) (1) (5) (4) pmbp bit (addr:00h, d5) " 0" or " 1" 0 clocks can be stopped. clock (3) (6) example: (2) addr:02h, data:60h (1) addr:00h, data:70h (3) addr:02h, data:e0h mono signal output (4) addr:02h, data:60h (5) addr:00h, data:40h (6) addr:02h, data:00h figure 44. ?min-amp ? speaker-amp? output sequence the clocks can be stopped when only mi n-amp and speaker-amp are operating. (1) power up min-amp and speaker-amp: pmbp = pmspk bits = ?0? o ?1? (2) disable the path of ?dac ? spk-amp?: dacs bit = ?0? enable the path of ?min ? spk-amp?: beeps bit = ?0? o ?1? (3) exit the power-save-mode of speaker-amp: sppsn bit = ?0? o ?1? ? (3) ? time depends on the time constant of external resistor and capacitor connected to min pin. if speaker-amp output is enabled be fore input of min-amp becomes stable, pop noise may occur. e.g. r=20k, c=0.1 p f: recommended wait time is more than 5 w = 10ms. (4) enter the power-save-mode of speaker-amp: sppsn bit = ?1? o ?0? (5) power down min-amp and speaker-amp: pmbp = pmspk bits = ?1? o ?0? (6) disable the path of ?min ? spk-amp?: beeps bit = ?1? o ?0?
[ak4646] ms0557-e-05 2011/01 - 74 - stereo line output fs3-0 bits (addr:05h, d5&d2-0) ovl/r7-0 bits (addr:0ah&0dh, d7-0) pmdac bit (addr:00h, d2) pmlo bit (addr:00h, d3) 1,111 0,000 91h 91h lout pin rout pin (1) (3) (4) (2) (9) normal output (6) (5) >300 ms (7) (8) >300 ms (10) pmbp bit (addr:00h, d5) lops bit (addr:03h, d6) dacl bit (addr:02h, d4) example: pll, master mode audio i/f format :msb justified (adc & dac) sampling frequency:44.1khz digital volume: 0db mgain1=spkg1=spkg0=beepl bits = ?0? (1) addr:05h, data:27h (2) addr:02h, data:10h (3) addr:0ah&0dh, data:91h (4) addr:03h, data:40h (5) addr:00h, data:6ch (6) addr:03h, data:00h playback (7) addr:03h, data:40h (8) addr:00h, data:40h (9) addr:02h, data:00h (10) addr:03h, data:00h figure 45. stereo lineout sequence at first, clocks should be supplied according to ?clock set up? sequence. (1) set up the sampling frequency (fs3-0 bits). when the ak4646 is pll mode, dac and stereo line-amp should be powered-up in consideration of pll lo ck time after the sampling frequency is changed. (2) set up the path of ?dac ? stereo line amp?: dacl bit = ?0? ? ?1? (3) set up the output digital volume (addr: 0ah and 0dh) when ovolc bit is ?1? (default), ovl 7-0 bits set the volume of both channels. after dac is powered-up, the digital volume changes from default value (0db) to the register setting value by the soft transition. (4) enter power-save mode of stereo line amp: lops bit = ?0? ? ?1? (5) power-up dac, min-amp and stereo line-a mp: pmdac = pmbp = pmlo bits = ?0? o ?1? the dac outputs invalid voltage for 67/fs = 1.52ms@fs = 44.1khz after powered-up, then it starts outputting normal voltage. lout and rout pins rise up to vcom vo ltage after pmlo bit is changed to ?1?. rise time is 300ms (max) at c=1 p f. (6) exit power-save mode of stereo line-amp: lops bit = ?1? ? ?0? lops bit should be set to ?0? after lout and rout pi ns rise up. stereo line-amp goes to normal operation by setting lops bit to ?0?. (7) enter power-save mode of stereo line-amp: lops bit: ?0? ? ?1? (8) power-down dac, min-amp and stereo line-amp: pmdac = pmbp = pmlo bits = ?1? o ?0? lout and rout pins fall down to avss. fall time is 300ms (max) at c=1 p f. (9) disable the path of ?dac ? stereo line-amp?: dacl bit = ?1? ? ?0? (10) exit power-save mode of stereo line-amp: lops bit = ?1? ? ?0? lops bit should be set to ?0? after lout and rout pins fall down.
[ak4646] ms0557-e-05 2011/01 - 75 - stop of clock master clock can be stopped wh en adc and dac are not used. 1. pll master mode external mcki pmpll bit (addr:01h, d0) mcko bit (addr:01h, d1) input (3) (1) (2) "0" or "1" example: audio i/f format: msb justified (adc & dac) bick frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz (3) stop an external mcki (1) (2) addr:01h, data:08h figure 46. clock stopping sequence (1) (1) power down pll: pmpll bit = ?1? ?0? (2) stop mcko clock: mcko bit = ?1? ?0? (3) stop an external master clock. 2. pll slave mode (lrck or bick pin) external bick pmpll bit (addr:01h, d0) input (1) (2) external lrck input (2) example audio i/f format : msb justified (adc & dac) pll reference clock: bick bick frequency: 64fs (1) addr:01h, data:00h (2) stop the external clocks figure 47. clock stopping sequence (2) (1) power down pll: pmpll bit = ?1? ?0? (2) stop the external bick and lrck clocks
[ak4646] ms0557-e-05 2011/01 - 76 - 3. pll slave (mcki pin) external mcki pmpll bit (addr:01h, d0) input (1) (2) mcko bit (addr:01h, d1) (1) example audio i/f format: msb justified (adc & dac) pll reference clock: mcki bick frequency: 64fs (1) addr:01h, data:00h (2) stop the external clocks figure 48. clock stopping sequence (3) (1) power down pll: pmpll bit = ?1? ?0? stop mcko output: mcko bit = ?1? ?0? (2) stop the external master clock. 4. ext slave mode external lrck input (1) external bick input (1) external mcki input (1) example audio i/f format :msb justified(adc & dac) input mcki frequency:1024fs (1) stop the external clocks figure 49. clock stopping sequence (4) (1) stop the external mcki, bick and lrck clocks. power supply current can be shut down (typ. 1 a) by stopping clocks and setting pmvcm bit = ?0? after all blocks except for vcom are powered-down. power suppl y current can be also shut down (typ. 1 a) by stopping clocks and setting pdn pin = ?l?. when pdn pin = ?l?, the registers are initialized.
[ak4646] ms0557-e-05 2011/01 - 77 - package (ak4646en) 32pin qfn (unit: mm) 4.75 0.10 5.00 0.10 4.75 0.10 0.50 0.23 24 17 25 1 16 1 0.01 0.08 32 8 9 c0.42 32 +0.07 -0.05 0.40 0.10 0.20 + 0.04 - 0.01 c exposed pad 3.5 5.00 0.10 0.85 0.05 c b a 0.10 m ab 3.5 note) the exposed pad on the bottom surface of the p ackage must be open or connected to the ground. material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatme nt: solder (pb free) plate
[ak4646] ms0557-e-05 2011/01 - 78 - package (ak4646ez) 32pin qfn (unit: mm) 2.4 0.1 0.4 0.18 0.05 0.00 min 0.05 max 0.65 max 2.4 0.1 1 9 16 25 4.0 0.1 4.0 0.1 0.45 0.10 a b 0.05 m 0.08 8 32 17 24 pin #1 id exposed pad 0.40 0.10 0.22 0.05 c0.3 note) the exposed pad on the bottom surface of the p ackage must be open or connected to the ground. note that the maximum operating ambient temperature is 70 c when it is open. material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatme nt: solder (pb free) plate
[ak4646] ms0557-e-05 2011/01 - 79 - marking (ak4646en) a k4646 x xxxx 1 a km xxxxx: date code identifier (5 digits) marking (ak4646ez) 4646 x xxx 1 xxxx: date code identifier (4 digits)
[ak4646] ms0557-e-05 2011/01 - 80 - revision history date (yy/mm/dd) revision reason page contents 07/05/14 02 first edition 10/01/07 03 specification change 39, 40 53, 60 fr bit was added. (alc fast recovery function enable bit) description change descriptions about the ak4646ez were added. 10/08/19 04 specification addition 7 recommended operating conditions avdd ? svdd was added: 0.8v (max) 11/01/19 05 error correction 9 analog characteristics note 18 was changed. ?when the dac input is -0.5dbfs in full-differential mode? was added. spkg1-0 bits = ?00? ?vout=0.94 x avdd? ?0.96 x avdd? spkg1-0 bits = ?10? ?vout=2.05 x avdd? ?1.52 x avdd? spkg1-0 bits = ?11? ?vout=2.58 x avdd? ?1.92 x avdd?
[ak4646] ms0557-e-05 2011/01 - 81 - important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application exampl es of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your e quipments. akm assumes no responsibility fo r any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the applica tion or use of such information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products , who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above conten t and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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